/*************************************************************************************
*************************************************************************************
*                                                                                   *
*  Revision      :  $Id: falcon_tsc_fields.h 924 2015-02-24 18:08:11Z eroes $ *
*                                                                                   *
*  Description   :  Register access macros for FALCON_TSC                           *
*                                                                                   *
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*      Broadcom Corporation                                                         *
*      5300 California Avenue                                                       *
*      Irvine, CA  92617                                                            *
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 */

/** @file falcon_tsc_fields.h
 * Register access macros for FALCON_TSC
 */

/* THIS FILE IS GENERATED USING AN AUTOMATED SCRIPT... PLEASE DO NOT EDIT THIS FILE DIRECTLY !!! */

#ifndef FALCON_TSC_FIELDS_H
#define FALCON_TSC_FIELDS_H
#define __ERR &__err

#define rdc_ams_pll_cal_aux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 0, 12, __ERR)
#define wrc_ams_pll_cal_aux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0xf000, 12, wr_val)
#define rdc_ams_pll_cal_off()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 4, 15, __ERR)
#define wrc_ams_pll_cal_off(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0800, 11, wr_val)
#define rdc_ams_pll_imode_iclkidrv1()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 5, 15, __ERR)
#define wrc_ams_pll_imode_iclkidrv1(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0400, 10, wr_val)
#define rdc_ams_pll_imax_iclkidrv1()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 6, 15, __ERR)
#define wrc_ams_pll_imax_iclkidrv1(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0200, 9, wr_val)
#define rdc_ams_pll_imin_iclkidrv1()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 7, 15, __ERR)
#define wrc_ams_pll_imin_iclkidrv1(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0100, 8, wr_val)
#define rdc_ams_pll_imode_iclkodrv1()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 8, 15, __ERR)
#define wrc_ams_pll_imode_iclkodrv1(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0080, 7, wr_val)
#define rdc_ams_pll_imax_iclkodrv1()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 9, 15, __ERR)
#define wrc_ams_pll_imax_iclkodrv1(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0040, 6, wr_val)
#define rdc_ams_pll_imin_iclkodrv1()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 10, 15, __ERR)
#define wrc_ams_pll_imin_iclkodrv1(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0020, 5, wr_val)
#define rdc_ams_pll_imode_iclkint()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 11, 15, __ERR)
#define wrc_ams_pll_imode_iclkint(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0010, 4, wr_val)
#define rdc_ams_pll_imax_iclkint()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 12, 15, __ERR)
#define wrc_ams_pll_imax_iclkint(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0008, 3, wr_val)
#define rdc_ams_pll_imin_iclkint()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 13, 15, __ERR)
#define wrc_ams_pll_imin_iclkint(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0004, 2, wr_val)
#define rdc_ams_pll_set_clk4tsc()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd110, 14, 14, __ERR)
#define wrc_ams_pll_set_clk4tsc(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd110, 0x0003, 0, wr_val)
#define rdc_ams_pll_enable_ftune()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd111, 0, 15, __ERR)
#define wrc_ams_pll_enable_ftune(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x8000, 15, wr_val)
#define rdc_ams_pll_reset()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd111, 1, 15, __ERR)
#define wrc_ams_pll_reset(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x4000, 14, wr_val)
#define rdc_ams_pll_ivco()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd111, 2, 13, __ERR)
#define wrc_ams_pll_ivco(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x3800, 11, wr_val)
#define rdc_ams_pll_vco_indicator()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd111, 5, 15, __ERR)
#define wrc_ams_pll_vco_indicator(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0400, 10, wr_val)
#define rdc_ams_pll_vcoictrl()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd111, 6, 14, __ERR)
#define wrc_ams_pll_vcoictrl(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0300, 8, wr_val)
#define rdc_ams_pll_spare_23_22()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd111, 8, 14, __ERR)
#define wrc_ams_pll_spare_23_22(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x00c0, 6, wr_val)
#define rdc_ams_pll_test_bg_opamp_bias()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd111, 10, 14, __ERR)
#define wrc_ams_pll_test_bg_opamp_bias(wr_val)        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0030, 4, wr_val)
#define rdc_ams_pll_drv_hv_disable()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd111, 12, 15, __ERR)
#define wrc_ams_pll_drv_hv_disable(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0008, 3, wr_val)
#define rdc_ams_pll_imode_ickgen()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd111, 13, 15, __ERR)
#define wrc_ams_pll_imode_ickgen(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0004, 2, wr_val)
#define rdc_ams_pll_imax_ickgen()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd111, 14, 15, __ERR)
#define wrc_ams_pll_imax_ickgen(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0002, 1, wr_val)
#define rdc_ams_pll_imin_ickgen()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd111, 15, 15, __ERR)
#define wrc_ams_pll_imin_ickgen(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd111, 0x0001, 0, wr_val)
#define rdc_ams_pll_imax_ick()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 0, 15, __ERR)
#define wrc_ams_pll_imax_ick(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x8000, 15, wr_val)
#define rdc_ams_pll_imode_ick()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 1, 15, __ERR)
#define wrc_ams_pll_imode_ick(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x4000, 14, wr_val)
#define rdc_ams_pll_imin_ick()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 2, 15, __ERR)
#define wrc_ams_pll_imin_ick(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x2000, 13, wr_val)
#define rdc_ams_pll_imax_icp()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 3, 15, __ERR)
#define wrc_ams_pll_imax_icp(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x1000, 12, wr_val)
#define rdc_ams_pll_imode_icp()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 4, 15, __ERR)
#define wrc_ams_pll_imode_icp(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0800, 11, wr_val)
#define rdc_ams_pll_imin_icp()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 5, 15, __ERR)
#define wrc_ams_pll_imin_icp(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0400, 10, wr_val)
#define rdc_ams_pll_imax_ibias()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 6, 15, __ERR)
#define wrc_ams_pll_imax_ibias(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0200, 9, wr_val)
#define rdc_ams_pll_imode_ibias()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 7, 15, __ERR)
#define wrc_ams_pll_imode_ibias(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0100, 8, wr_val)
#define rdc_ams_pll_imin_ibias()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 8, 15, __ERR)
#define wrc_ams_pll_imin_ibias(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0080, 7, wr_val)
#define rdc_ams_pll_refh_pll()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 9, 15, __ERR)
#define wrc_ams_pll_refh_pll(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0040, 6, wr_val)
#define rdc_ams_pll_refl_pll()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 10, 15, __ERR)
#define wrc_ams_pll_refl_pll(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0020, 5, wr_val)
#define rdc_ams_pll_iqp()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 11, 12, __ERR)
#define wrc_ams_pll_iqp(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x001e, 1, wr_val)
#define rdc_ams_pll_en_hrz()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd112, 15, 15, __ERR)
#define wrc_ams_pll_en_hrz(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd112, 0x0001, 0, wr_val)
#define rdc_ams_pll_test_rx()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 0, 15, __ERR)
#define wrc_ams_pll_test_rx(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x8000, 15, wr_val)
#define rdc_ams_pll_test_pll()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 1, 15, __ERR)
#define wrc_ams_pll_test_pll(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x4000, 14, wr_val)
#define rdc_ams_pll_test_vc()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 2, 15, __ERR)
#define wrc_ams_pll_test_vc(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x2000, 13, wr_val)
#define rdc_ams_pll_test_vref()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 3, 15, __ERR)
#define wrc_ams_pll_test_vref(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x1000, 12, wr_val)
#define rdc_ams_pll_imax_iop()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 4, 15, __ERR)
#define wrc_ams_pll_imax_iop(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0800, 11, wr_val)
#define rdc_ams_pll_imode_iop()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 5, 15, __ERR)
#define wrc_ams_pll_imode_iop(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0400, 10, wr_val)
#define rdc_ams_pll_imin_iop()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 6, 15, __ERR)
#define wrc_ams_pll_imin_iop(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0200, 9, wr_val)
#define rdc_ams_pll_imax_icomp()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 7, 15, __ERR)
#define wrc_ams_pll_imax_icomp(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0100, 8, wr_val)
#define rdc_ams_pll_imode_icomp()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 8, 15, __ERR)
#define wrc_ams_pll_imode_icomp(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0080, 7, wr_val)
#define rdc_ams_pll_imin_icomp()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 9, 15, __ERR)
#define wrc_ams_pll_imin_icomp(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0040, 6, wr_val)
#define rdc_ams_pll_imax_icmldiv()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 10, 15, __ERR)
#define wrc_ams_pll_imax_icmldiv(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0020, 5, wr_val)
#define rdc_ams_pll_imode_icmldiv()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 11, 15, __ERR)
#define wrc_ams_pll_imode_icmldiv(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0010, 4, wr_val)
#define rdc_ams_pll_imin_icmldiv()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 12, 15, __ERR)
#define wrc_ams_pll_imin_icmldiv(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0008, 3, wr_val)
#define rdc_ams_pll_imax_irxclkbuf()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 13, 15, __ERR)
#define wrc_ams_pll_imax_irxclkbuf(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0004, 2, wr_val)
#define rdc_ams_pll_imode_irxclkbuf()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 14, 15, __ERR)
#define wrc_ams_pll_imode_irxclkbuf(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0002, 1, wr_val)
#define rdc_ams_pll_imin_irxclkbuf()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd113, 15, 15, __ERR)
#define wrc_ams_pll_imin_irxclkbuf(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd113, 0x0001, 0, wr_val)
#define rdc_ams_pll_force_rescal()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd114, 0, 15, __ERR)
#define wrc_ams_pll_force_rescal(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x8000, 15, wr_val)
#define rdc_ams_pll_force_kvh_bw()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd114, 1, 15, __ERR)
#define wrc_ams_pll_force_kvh_bw(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x4000, 14, wr_val)
#define rdc_ams_pll_kvh_force()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd114, 2, 14, __ERR)
#define wrc_ams_pll_kvh_force(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x3000, 12, wr_val)
#define rdc_ams_pll_vddr_bgb()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd114, 4, 15, __ERR)
#define wrc_ams_pll_vddr_bgb(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x0800, 11, wr_val)
#define rdc_ams_pll_comp_vth()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd114, 5, 15, __ERR)
#define wrc_ams_pll_comp_vth(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x0400, 10, wr_val)
#define rdc_ams_pll_pll2rx_clkbw()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd114, 6, 14, __ERR)
#define wrc_ams_pll_pll2rx_clkbw(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x0300, 8, wr_val)
#define rdc_ams_pll_bgr_ctatadj()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd114, 8, 12, __ERR)
#define wrc_ams_pll_bgr_ctatadj(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x00f0, 4, wr_val)
#define rdc_ams_pll_bgr_ptatadj()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd114, 12, 12, __ERR)
#define wrc_ams_pll_bgr_ptatadj(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd114, 0x000f, 0, wr_val)
#define rdc_ams_pll_mix3p1c_calr_ptatadj()            _falcon_tsc_pmd_rde_field_byte(pa, 0xd115, 0, 11, __ERR)
#define wrc_ams_pll_mix3p1c_calr_ptatadj(wr_val)      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0xf800, 11, wr_val)
#define rdc_ams_pll_mix3p1c_calr_ctatadj()            _falcon_tsc_pmd_rde_field_byte(pa, 0xd115, 5, 11, __ERR)
#define wrc_ams_pll_mix3p1c_calr_ctatadj(wr_val)      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x07c0, 6, wr_val)
#define rdc_ams_pll_test_pnp()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd115, 10, 14, __ERR)
#define wrc_ams_pll_test_pnp(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x0030, 4, wr_val)
#define rdc_ams_pll_vbypass()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd115, 12, 15, __ERR)
#define wrc_ams_pll_vbypass(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x0008, 3, wr_val)
#define rdc_ams_pll_bgint()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd115, 13, 15, __ERR)
#define wrc_ams_pll_bgint(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x0004, 2, wr_val)
#define rdc_ams_pll_bgip()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd115, 14, 15, __ERR)
#define wrc_ams_pll_bgip(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x0002, 1, wr_val)
#define rdc_ams_pll_test_port_max_amplitude()         _falcon_tsc_pmd_rde_field_byte(pa, 0xd115, 15, 15, __ERR)
#define wrc_ams_pll_test_port_max_amplitude(wr_val)   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd115, 0x0001, 0, wr_val)
#define rdc_ams_pll_mix1p2cr_ptatadj()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd116, 0, 11, __ERR)
#define wrc_ams_pll_mix1p2cr_ptatadj(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd116, 0xf800, 11, wr_val)
#define rdc_ams_pll_mix1p2cr_ctatadj()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd116, 5, 11, __ERR)
#define wrc_ams_pll_mix1p2cr_ctatadj(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd116, 0x07c0, 6, wr_val)
#define rdc_ams_pll_spare_101_96()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd116, 10, 10, __ERR)
#define wrc_ams_pll_spare_101_96(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd116, 0x003f, 0, wr_val)
#define rdc_ams_pll_mix3p1cr_ptatadj()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd117, 0, 11, __ERR)
#define wrc_ams_pll_mix3p1cr_ptatadj(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd117, 0xf800, 11, wr_val)
#define rdc_ams_pll_mix3p1cr_ctatadj()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd117, 5, 11, __ERR)
#define wrc_ams_pll_mix3p1cr_ctatadj(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd117, 0x07c0, 6, wr_val)
#define rdc_ams_pll_spare_117_112()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd117, 10, 10, __ERR)
#define wrc_ams_pll_spare_117_112(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd117, 0x003f, 0, wr_val)
#define rdc_ams_pll_kvh()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd119, 0, 14, __ERR)
#define rdc_ams_pll_range()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd119, 2, 8, __ERR)
#define rdc_ams_pll_low()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd119, 10, 15, __ERR)
#define rdc_ams_pll_ndiv()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd119, 12, 12, __ERR)
#define rd_ams_rx_peaking_filter_ibias()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c0, 0, 13, __ERR)
#define wr_ams_rx_peaking_filter_ibias(wr_val)        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0xe000, 13, wr_val)
#define rd_ams_rx_dc_couple()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c0, 3, 15, __ERR)
#define wr_ams_rx_dc_couple(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x1000, 12, wr_val)
#define rd_ams_rx_dfe_hgain_en()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c0, 4, 15, __ERR)
#define wr_ams_rx_dfe_hgain_en(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0800, 11, wr_val)
#define rd_ams_rx_eq_lz_en()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c0, 5, 15, __ERR)
#define wr_ams_rx_eq_lz_en(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0400, 10, wr_val)
#define rd_ams_rx_vga_10g_bw()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c0, 6, 15, __ERR)
#define wr_ams_rx_vga_10g_bw(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0200, 9, wr_val)
#define rd_ams_rx_tport_en()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c0, 7, 15, __ERR)
#define wr_ams_rx_tport_en(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0100, 8, wr_val)
#define rd_ams_rx_sigdet_bypass()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c0, 8, 15, __ERR)
#define wr_ams_rx_sigdet_bypass(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0080, 7, wr_val)
#define rd_ams_rx_sigdet_pwrdn()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c0, 9, 15, __ERR)
#define wr_ams_rx_sigdet_pwrdn(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0040, 6, wr_val)
#define rd_ams_rx_sigdet_threshold()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c0, 10, 13, __ERR)
#define wr_ams_rx_sigdet_threshold(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0038, 3, wr_val)
#define rd_ams_rx_master_diodes_ibias()               _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c0, 13, 13, __ERR)
#define wr_ams_rx_master_diodes_ibias(wr_val)         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c0, 0x0007, 0, wr_val)
#define rd_ams_rx_cm_voltage_ibias()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c1, 0, 13, __ERR)
#define wr_ams_rx_cm_voltage_ibias(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0xe000, 13, wr_val)
#define rd_ams_rx_vga3_ibias()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c1, 3, 13, __ERR)
#define wr_ams_rx_vga3_ibias(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x1c00, 10, wr_val)
#define rd_ams_rx_vga2_ibias()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c1, 6, 13, __ERR)
#define wr_ams_rx_vga2_ibias(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0380, 7, wr_val)
#define rd_ams_rx_vga1_ibias()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c1, 9, 13, __ERR)
#define wr_ams_rx_vga1_ibias(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0070, 4, wr_val)
#define rd_ams_rx_vga0_ibias()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c1, 12, 13, __ERR)
#define wr_ams_rx_vga0_ibias(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x000e, 1, wr_val)
#define rd_ams_rx_spare_16()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c1, 15, 15, __ERR)
#define wr_ams_rx_spare_16(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c1, 0x0001, 0, wr_val)
#define rd_ams_rx_pwrdn_ftap()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c2, 0, 15, __ERR)
#define wr_ams_rx_pwrdn_ftap(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x8000, 15, wr_val)
#define rd_ams_rx_sigdet_power_save()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c2, 1, 15, __ERR)
#define wr_ams_rx_sigdet_power_save(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x4000, 14, wr_val)
#define rd_ams_rx_pd_ch_p1()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c2, 2, 15, __ERR)
#define wr_ams_rx_pd_ch_p1(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x2000, 13, wr_val)
#define rd_ams_rx_sel_th4dfe()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c2, 3, 14, __ERR)
#define wr_ams_rx_sel_th4dfe(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x1800, 11, wr_val)
#define rd_ams_rx_sel_ugbw()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c2, 5, 14, __ERR)
#define wr_ams_rx_sel_ugbw(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x0600, 9, wr_val)
#define rd_ams_rx_dfe_tap_weight_ibias()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c2, 7, 13, __ERR)
#define wr_ams_rx_dfe_tap_weight_ibias(wr_val)        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x01c0, 6, wr_val)
#define rd_ams_rx_phase_interpolators_ibias()         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c2, 10, 13, __ERR)
#define wr_ams_rx_phase_interpolators_ibias(wr_val)   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x0038, 3, wr_val)
#define rd_ams_rx_sigdet_ibias()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c2, 13, 13, __ERR)
#define wr_ams_rx_sigdet_ibias(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c2, 0x0007, 0, wr_val)
#define rd_ams_rx_spare_63()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c3, 0, 15, __ERR)
#define wr_ams_rx_spare_63(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x8000, 15, wr_val)
#define rd_ams_rx_dfe_slicer_ibias()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c3, 1, 13, __ERR)
#define wr_ams_rx_dfe_slicer_ibias(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x7000, 12, wr_val)
#define rd_ams_rx_dfe_sum_buf_ibias()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c3, 4, 13, __ERR)
#define wr_ams_rx_dfe_sum_buf_ibias(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x0e00, 9, wr_val)
#define rd_ams_rx_offset_correction_ibias()           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c3, 7, 13, __ERR)
#define wr_ams_rx_offset_correction_ibias(wr_val)     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x01c0, 6, wr_val)
#define rd_ams_rx_dll_ibias()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c3, 10, 13, __ERR)
#define wr_ams_rx_dll_ibias(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x0038, 3, wr_val)
#define rd_ams_rx_met_r_ibias()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c3, 13, 13, __ERR)
#define wr_ams_rx_met_r_ibias(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c3, 0x0007, 0, wr_val)
#define rd_ams_rx_vga1_rescal_mux()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c4, 0, 11, __ERR)
#define wr_ams_rx_vga1_rescal_mux(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c4, 0xf800, 11, wr_val)
#define rd_ams_rx_vga0_rescal_mux()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c4, 5, 11, __ERR)
#define wr_ams_rx_vga0_rescal_mux(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c4, 0x07c0, 6, wr_val)
#define rd_ams_rx_tbd_ibias()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c4, 10, 13, __ERR)
#define wr_ams_rx_tbd_ibias(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c4, 0x0038, 3, wr_val)
#define rd_ams_rx_dfe_slicer_cal_ibias()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c4, 13, 13, __ERR)
#define wr_ams_rx_dfe_slicer_cal_ibias(wr_val)        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c4, 0x0007, 0, wr_val)
#define rd_ams_rx_spare_95()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c5, 0, 15, __ERR)
#define wr_ams_rx_spare_95(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c5, 0x8000, 15, wr_val)
#define rd_ams_rx_spare_94_90()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c5, 1, 11, __ERR)
#define wr_ams_rx_spare_94_90(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c5, 0x7c00, 10, wr_val)
#define rd_ams_rx_vga3_rescal_mux()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c5, 6, 11, __ERR)
#define wr_ams_rx_vga3_rescal_mux(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c5, 0x03e0, 5, wr_val)
#define rd_ams_rx_vga2_rescal_mux()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c5, 11, 11, __ERR)
#define wr_ams_rx_vga2_rescal_mux(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c5, 0x001f, 0, wr_val)
#define rd_ams_rx_spare_111_104()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c6, 0, 8, __ERR)
#define wr_ams_rx_spare_111_104(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c6, 0xff00, 8, wr_val)
#define rd_ams_rx_offset_correction_rescal_mux()      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c6, 8, 12, __ERR)
#define wr_ams_rx_offset_correction_rescal_mux(wr_val)  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c6, 0x00f0, 4, wr_val)
#define rd_ams_rx_peaking_filter_rescal_mux()         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c6, 12, 12, __ERR)
#define wr_ams_rx_peaking_filter_rescal_mux(wr_val)   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c6, 0x000f, 0, wr_val)
#define rd_ams_rx_vga_step_mode()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c7, 0, 14, __ERR)
#define wr_ams_rx_vga_step_mode(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0xc000, 14, wr_val)
#define rd_ams_rx_vga_low_gain()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c7, 2, 14, __ERR)
#define wr_ams_rx_vga_low_gain(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x3000, 12, wr_val)
#define rd_ams_rx_spare_123()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c7, 4, 15, __ERR)
#define wr_ams_rx_spare_123(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x0800, 11, wr_val)
#define rd_ams_rx_short_vga_output()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c7, 5, 15, __ERR)
#define wr_ams_rx_short_vga_output(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x0400, 10, wr_val)
#define rd_ams_rx_rx_offset_pd()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c7, 6, 15, __ERR)
#define wr_ams_rx_rx_offset_pd(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x0200, 9, wr_val)
#define rd_ams_rx_dc_offset_range()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c7, 7, 15, __ERR)
#define wr_ams_rx_dc_offset_range(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x0100, 8, wr_val)
#define rd_ams_rx_force_dc_offset()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c7, 8, 15, __ERR)
#define wr_ams_rx_force_dc_offset(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x0080, 7, wr_val)
#define rd_ams_rx_dc_offset()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c7, 9, 9, __ERR)
#define wr_ams_rx_dc_offset(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c7, 0x007f, 0, wr_val)
#define rd_ams_rx_spare_143_142()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c8, 0, 14, __ERR)
#define wr_ams_rx_spare_143_142(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c8, 0xc000, 14, wr_val)
#define rd_ams_rx_dac4ck_phs()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c8, 2, 10, __ERR)
#define wr_ams_rx_dac4ck_phs(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c8, 0x3f00, 8, wr_val)
#define rd_ams_rx_spare_135_134()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c8, 8, 14, __ERR)
#define wr_ams_rx_spare_135_134(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c8, 0x00c0, 6, wr_val)
#define rd_ams_rx_dac4ck_lms()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c8, 10, 10, __ERR)
#define wr_ams_rx_dac4ck_lms(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c8, 0x003f, 0, wr_val)
#define rd_ams_rx_spare_159()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c9, 0, 15, __ERR)
#define wr_ams_rx_spare_159(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x8000, 15, wr_val)
#define rd_ams_rx_d2c_clkbuf_ibias()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c9, 1, 13, __ERR)
#define wr_ams_rx_d2c_clkbuf_ibias(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x7000, 12, wr_val)
#define rd_ams_rx_sel_d2clp()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c9, 4, 15, __ERR)
#define wr_ams_rx_sel_d2clp(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x0800, 11, wr_val)
#define rd_ams_rx_en_tap9delay()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c9, 5, 15, __ERR)
#define wr_ams_rx_en_tap9delay(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x0400, 10, wr_val)
#define rd_ams_rx_clk_bw_ctrl()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c9, 6, 14, __ERR)
#define wr_ams_rx_clk_bw_ctrl(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x0300, 8, wr_val)
#define rd_ams_rx_spare_151_150()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c9, 8, 14, __ERR)
#define wr_ams_rx_spare_151_150(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x00c0, 6, wr_val)
#define rd_ams_rx_dac4ck_dat()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0c9, 10, 10, __ERR)
#define wr_ams_rx_dac4ck_dat(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0c9, 0x003f, 0, wr_val)
#define rd_ams_rx_sigdet()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd0cb, 0, 15, __ERR)
#define rd_ams_rx_pf_ctrl_gray()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0cb, 1, 12, __ERR)
#define rd_ams_rx_tap1_data_thresh_sel_gray()         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0cb, 5, 10, __ERR)
#define rd_ams_rx_vga_ctrl_gray()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0cb, 11, 11, __ERR)
#define rd_ams_tx_cal_aux()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d0, 0, 12, __ERR)
#define wr_ams_tx_cal_aux(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0xf000, 12, wr_val)
#define rd_ams_tx_cal_off()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d0, 4, 15, __ERR)
#define wr_ams_tx_cal_off(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0800, 11, wr_val)
#define rd_ams_tx_dcc_dis()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d0, 5, 15, __ERR)
#define wr_ams_tx_dcc_dis(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0400, 10, wr_val)
#define rd_ams_tx_dcc_sel()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d0, 6, 15, __ERR)
#define wr_ams_tx_dcc_sel(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0200, 9, wr_val)
#define rd_ams_tx_vddr_bgb()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d0, 7, 15, __ERR)
#define wr_ams_tx_vddr_bgb(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0100, 8, wr_val)
#define rd_ams_tx_ticksel()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d0, 8, 14, __ERR)
#define wr_ams_tx_ticksel(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x00c0, 6, wr_val)
#define rd_ams_tx_test_data()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d0, 10, 14, __ERR)
#define wr_ams_tx_test_data(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0030, 4, wr_val)
#define rd_ams_tx_spare_3_1()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d0, 12, 13, __ERR)
#define wr_ams_tx_spare_3_1(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x000e, 1, wr_val)
#define rd_ams_tx_spare_0()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d0, 15, 15, __ERR)
#define wr_ams_tx_spare_0(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d0, 0x0001, 0, wr_val)
#define rd_ams_tx_spare_31()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d1, 0, 15, __ERR)
#define wr_ams_tx_spare_31(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x8000, 15, wr_val)
#define rd_ams_tx_sel_emph_mode()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d1, 1, 15, __ERR)
#define wr_ams_tx_sel_emph_mode(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x4000, 14, wr_val)
#define rd_ams_tx_ldo_vref()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d1, 2, 14, __ERR)
#define wr_ams_tx_ldo_vref(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x3000, 12, wr_val)
#define rd_ams_tx_ildo()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d1, 4, 13, __ERR)
#define wr_ams_tx_ildo(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0e00, 9, wr_val)
#define rd_ams_tx_icml()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d1, 7, 13, __ERR)
#define wr_ams_tx_icml(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x01c0, 6, wr_val)
#define rd_ams_tx_spare_21_19()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d1, 10, 13, __ERR)
#define wr_ams_tx_spare_21_19(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0038, 3, wr_val)
#define rd_ams_tx_ibias()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d1, 13, 13, __ERR)
#define wr_ams_tx_ibias(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d1, 0x0007, 0, wr_val)
#define rd_ams_tx_elec_idle_aux()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d2, 0, 15, __ERR)
#define wr_ams_tx_elec_idle_aux(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x8000, 15, wr_val)
#define rd_ams_tx_drivermode()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d2, 1, 14, __ERR)
#define wr_ams_tx_drivermode(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x6000, 13, wr_val)
#define rd_ams_tx_sign_post2()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d2, 3, 15, __ERR)
#define wr_ams_tx_sign_post2(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x1000, 12, wr_val)
#define rd_ams_tx_post2_coef()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d2, 4, 12, __ERR)
#define wr_ams_tx_post2_coef(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x0f00, 8, wr_val)
#define rd_ams_tx_sign_post3()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d2, 8, 15, __ERR)
#define wr_ams_tx_sign_post3(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x0080, 7, wr_val)
#define rd_ams_tx_post3_coef()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d2, 9, 13, __ERR)
#define wr_ams_tx_post3_coef(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x0070, 4, wr_val)
#define rd_ams_tx_amp_ctl()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d2, 12, 12, __ERR)
#define wr_ams_tx_amp_ctl(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0d2, 0x000f, 0, wr_val)
#define rd_ams_tx_spare_63_48()                       _falcon_tsc_pmd_rde_reg(pa, 0xd0d3, __ERR)
#define wr_ams_tx_spare_63_48(wr_val)                 falcon_tsc_pmd_wr_reg(pa, 0xd0d3, wr_val)
#define rd_ams_tx_lane_id()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d8, 0, 14, __ERR)
#define rd_ams_tx_drv_hv_disable()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d8, 3, 15, __ERR)
#define rd_ams_tx_ana_rescal()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d8, 4, 12, __ERR)
#define rd_ams_tx_version_id()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0d8, 8, 8, __ERR)
#define rd_osr_mode_frc()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b0, 0, 15, __ERR)
#define wr_osr_mode_frc(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x8000, 15, wr_val)
#define rd_osr_mode_frc_val()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b0, 12, 12, __ERR)
#define wr_osr_mode_frc_val(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b0, 0x000f, 0, wr_val)
#define rd_afe_sigdet_pwrdn()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b1, 11, 15, __ERR)
#define wr_afe_sigdet_pwrdn(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0010, 4, wr_val)
#define rd_ln_tx_s_pwrdn()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b1, 12, 15, __ERR)
#define wr_ln_tx_s_pwrdn(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0008, 3, wr_val)
#define rd_ln_rx_s_pwrdn()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b1, 13, 15, __ERR)
#define wr_ln_rx_s_pwrdn(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0004, 2, wr_val)
#define rd_ln_dp_s_rstb()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b1, 14, 15, __ERR)
#define wr_ln_dp_s_rstb(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b1, 0x0002, 1, wr_val)
#define rd_ln_s_rstb()                                _falcon_tsc_pmd_rde_field_byte(pa, 0xd0be, 15, 15, __ERR)
#define wr_ln_s_rstb(wr_val)                          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0be, 0x0001, 0, wr_val)
#define rd_pmd_rx_clk_vld_frc_val()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b7, 11, 15, __ERR)
#define wr_pmd_rx_clk_vld_frc_val(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b7, 0x0010, 4, wr_val)
#define rd_pmd_rx_clk_vld_frc()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b7, 12, 15, __ERR)
#define wr_pmd_rx_clk_vld_frc(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b7, 0x0008, 3, wr_val)
#define rd_ln_rx_s_comclk_frc_on()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b7, 13, 15, __ERR)
#define wr_ln_rx_s_comclk_frc_on(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b7, 0x0004, 2, wr_val)
#define rd_ln_rx_s_comclk_sel()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b7, 14, 15, __ERR)
#define wr_ln_rx_s_comclk_sel(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b7, 0x0002, 1, wr_val)
#define rd_ln_rx_s_clkgate_frc_on()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b7, 15, 15, __ERR)
#define wr_ln_rx_s_clkgate_frc_on(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b7, 0x0001, 0, wr_val)
#define rd_ln_tx_dp_s_rstb()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b4, 6, 15, __ERR)
#define wr_ln_tx_dp_s_rstb(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x0200, 9, wr_val)
#define rd_ln_tx_s_rstb()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b4, 7, 15, __ERR)
#define wr_ln_tx_s_rstb(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x0100, 8, wr_val)
#define rd_sigdet_dp_rstb_en()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b4, 13, 15, __ERR)
#define wr_sigdet_dp_rstb_en(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x0004, 2, wr_val)
#define rd_ln_rx_dp_s_rstb()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b4, 14, 15, __ERR)
#define wr_ln_rx_dp_s_rstb(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x0002, 1, wr_val)
#define rd_ln_rx_s_rstb()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b4, 15, 15, __ERR)
#define wr_ln_rx_s_rstb(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b4, 0x0001, 0, wr_val)
#define rd_afe_rx_rclk20_pwrdn_frc_val()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b2, 6, 15, __ERR)
#define wr_afe_rx_rclk20_pwrdn_frc_val(wr_val)        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0200, 9, wr_val)
#define rd_afe_rx_rclk20_pwrdn_frc()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b2, 7, 15, __ERR)
#define wr_afe_rx_rclk20_pwrdn_frc(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0100, 8, wr_val)
#define rd_afe_tx_reset_frc_val()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b2, 8, 15, __ERR)
#define wr_afe_tx_reset_frc_val(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0080, 7, wr_val)
#define rd_afe_tx_reset_frc()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b2, 9, 15, __ERR)
#define wr_afe_tx_reset_frc(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0040, 6, wr_val)
#define rd_afe_tx_pwrdn_frc_val()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b2, 10, 15, __ERR)
#define wr_afe_tx_pwrdn_frc_val(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0020, 5, wr_val)
#define rd_afe_tx_pwrdn_frc()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b2, 11, 15, __ERR)
#define wr_afe_tx_pwrdn_frc(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0010, 4, wr_val)
#define rd_afe_rx_reset_frc_val()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b2, 12, 15, __ERR)
#define wr_afe_rx_reset_frc_val(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0008, 3, wr_val)
#define rd_afe_rx_reset_frc()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b2, 13, 15, __ERR)
#define wr_afe_rx_reset_frc(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0004, 2, wr_val)
#define rd_afe_rx_pwrdn_frc_val()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b2, 14, 15, __ERR)
#define wr_afe_rx_pwrdn_frc_val(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0002, 1, wr_val)
#define rd_afe_rx_pwrdn_frc()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b2, 15, 15, __ERR)
#define wr_afe_rx_pwrdn_frc(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b2, 0x0001, 0, wr_val)
#define rd_pmd_ln_tx_h_pwrdn_pkill()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b3, 12, 15, __ERR)
#define wr_pmd_ln_tx_h_pwrdn_pkill(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0008, 3, wr_val)
#define rd_pmd_ln_rx_h_pwrdn_pkill()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b3, 13, 15, __ERR)
#define wr_pmd_ln_rx_h_pwrdn_pkill(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0004, 2, wr_val)
#define rd_pmd_ln_dp_h_rstb_pkill()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b3, 14, 15, __ERR)
#define wr_pmd_ln_dp_h_rstb_pkill(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0002, 1, wr_val)
#define rd_pmd_ln_h_rstb_pkill()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b3, 15, 15, __ERR)
#define wr_pmd_ln_h_rstb_pkill(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b3, 0x0001, 0, wr_val)
#define rd_pmd_lane_mode()                            _falcon_tsc_pmd_rde_reg(pa, 0xd0b8, __ERR)
#define rd_uc_ack_lane_dp_reset()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b5, 14, 15, __ERR)
#define wr_uc_ack_lane_dp_reset(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b5, 0x0002, 1, wr_val)
#define rd_uc_ack_lane_cfg_done()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b5, 15, 15, __ERR)
#define wr_uc_ack_lane_cfg_done(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b5, 0x0001, 0, wr_val)
#define rd_lane_dp_reset_state()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b9, 13, 13, __ERR)
#define rd_lane_reg_reset_occurred()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd0b6, 15, 15, __ERR)
#define wr_lane_reg_reset_occurred(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0b6, 0x0001, 0, wr_val)
#define rd_lane_multicast_mask_control()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd0ba, 15, 15, __ERR)
#define wr_lane_multicast_mask_control(wr_val)        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0ba, 0x0001, 0, wr_val)
#define rd_osr_mode()                                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd0bb, 12, 12, __ERR)
#define rd_osr_mode_pin()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd0bc, 12, 12, __ERR)
#define rd_cl93n72_ieee_lp_coeff_update()             _falcon_tsc_pmd_rde_reg(pa, 0x0098, __ERR)
#define rd_cl93n72_ieee_lp_status_report()            _falcon_tsc_pmd_rde_reg(pa, 0x0099, __ERR)
#define rd_cl93n72_ieee_training_enable()             _falcon_tsc_pmd_rde_field_byte(pa, 0x0096, 14, 15, __ERR)
#define wr_cl93n72_ieee_training_enable(wr_val)       _falcon_tsc_pmd_mwr_reg_byte(pa, 0x0096, 0x0002, 1, wr_val)
#define rd_cl93n72_ieee_restart_training()            _falcon_tsc_pmd_rde_field_byte(pa, 0x0096, 15, 15, __ERR)
#define wr_cl93n72_ieee_restart_training(wr_val)      _falcon_tsc_pmd_mwr_reg_byte(pa, 0x0096, 0x0001, 0, wr_val)
#define rd_cl93n72_ieee_training_failure()            _falcon_tsc_pmd_rde_field_byte(pa, 0x0097, 12, 15, __ERR)
#define rd_cl93n72_ieee_training_status()             _falcon_tsc_pmd_rde_field_byte(pa, 0x0097, 13, 15, __ERR)
#define rd_cl93n72_ieee_frame_lock()                  _falcon_tsc_pmd_rde_field_byte(pa, 0x0097, 14, 15, __ERR)
#define rd_cl93n72_ieee_receiver_status()             _falcon_tsc_pmd_rde_field_byte(pa, 0x0097, 15, 15, __ERR)
#define rd_cl93n72_ieee_ld_coeff_update()             _falcon_tsc_pmd_rde_reg(pa, 0x009a, __ERR)
#define rd_cl93n72_ieee_ld_status_report()            _falcon_tsc_pmd_rde_reg(pa, 0x009b, __ERR)
#define rd_cl93n72_rx_signal_ok()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd080, 13, 15, __ERR)
#define wr_cl93n72_rx_signal_ok(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd080, 0x0004, 2, wr_val)
#define rd_cl93n72_tr_coarse_lock()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd080, 14, 15, __ERR)
#define wr_cl93n72_tr_coarse_lock(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd080, 0x0002, 1, wr_val)
#define rd_cl93n72_rx_training_en()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd080, 15, 15, __ERR)
#define wr_cl93n72_rx_training_en(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd080, 0x0001, 0, wr_val)
#define rd_cl93n72_bad_marker_cnt()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd081, 9, 13, __ERR)
#define wr_cl93n72_bad_marker_cnt(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd081, 0x0070, 4, wr_val)
#define rd_cl93n72_good_marker_cnt()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd081, 14, 14, __ERR)
#define wr_cl93n72_good_marker_cnt(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd081, 0x0003, 0, wr_val)
#define rd_cl93n72_frame_consistency_chk_en()         _falcon_tsc_pmd_rde_field_byte(pa, 0xd082, 6, 15, __ERR)
#define wr_cl93n72_frame_consistency_chk_en(wr_val)   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0200, 9, wr_val)
#define rd_cl93n72_rx_dp_ln_clk_en()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd082, 7, 15, __ERR)
#define wr_cl93n72_rx_dp_ln_clk_en(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0100, 8, wr_val)
#define rd_cl93n72_ppm_offset_en()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd082, 8, 15, __ERR)
#define wr_cl93n72_ppm_offset_en(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0080, 7, wr_val)
#define rd_cl93n72_strict_marker_chk()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd082, 9, 15, __ERR)
#define wr_cl93n72_strict_marker_chk(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0040, 6, wr_val)
#define rd_cl93n72_strict_dme_chk()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd082, 10, 15, __ERR)
#define wr_cl93n72_strict_dme_chk(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0020, 5, wr_val)
#define rd_cl93n72_dme_cell_boundary_chk()            _falcon_tsc_pmd_rde_field_byte(pa, 0xd082, 11, 15, __ERR)
#define wr_cl93n72_dme_cell_boundary_chk(wr_val)      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x0010, 4, wr_val)
#define rd_cl93n72_ctrl_frame_dly()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd082, 12, 12, __ERR)
#define wr_cl93n72_ctrl_frame_dly(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd082, 0x000f, 0, wr_val)
#define rd_cl93n72_frame_lock()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd083, 15, 15, __ERR)
#define rd_cl93n72_micro_frame_lock_int_en()          _falcon_tsc_pmd_rde_field_byte(pa, 0xd084, 13, 15, __ERR)
#define wr_cl93n72_micro_frame_lock_int_en(wr_val)    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0004, 2, wr_val)
#define rd_cl93n72_micro_status_chg_int_en()          _falcon_tsc_pmd_rde_field_byte(pa, 0xd084, 14, 15, __ERR)
#define wr_cl93n72_micro_status_chg_int_en(wr_val)    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0002, 1, wr_val)
#define rd_cl93n72_micro_update_chg_int_en()          _falcon_tsc_pmd_rde_field_byte(pa, 0xd084, 15, 15, __ERR)
#define wr_cl93n72_micro_update_chg_int_en(wr_val)    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd084, 0x0001, 0, wr_val)
#define rd_cl93n72_micro_update_chg_lstatus()         _falcon_tsc_pmd_rde_field_byte(pa, 0xd085, 15, 15, __ERR)
#define rd_cl93n72_micro_frame_lock_lstatus()         _falcon_tsc_pmd_rde_field_byte(pa, 0xd086, 14, 15, __ERR)
#define rd_cl93n72_micro_status_chg_lstatus()         _falcon_tsc_pmd_rde_field_byte(pa, 0xd086, 15, 15, __ERR)
#define rd_cl93n72_xmt_update_page()                  _falcon_tsc_pmd_rde_reg(pa, 0xd090, __ERR)
#define wr_cl93n72_xmt_update_page(wr_val)            falcon_tsc_pmd_wr_reg(pa, 0xd090, wr_val)
#define rd_cl93n72_ld_xmt_status_page()               _falcon_tsc_pmd_rde_reg(pa, 0xd091, __ERR)
#define wr_cl93n72_ld_xmt_status_page(wr_val)         falcon_tsc_pmd_wr_reg(pa, 0xd091, wr_val)
#define rd_cl93n72_sw_remote_rx_ready()               _falcon_tsc_pmd_rde_field_byte(pa, 0xd092, 13, 15, __ERR)
#define wr_cl93n72_sw_remote_rx_ready(wr_val)         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0004, 2, wr_val)
#define rd_cl93n72_sw_rx_trained()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd092, 15, 15, __ERR)
#define wr_cl93n72_sw_rx_trained(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0001, 0, wr_val)
#define rd_cl93n72_sw_frame_lock()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd092, 14, 15, __ERR)
#define wr_cl93n72_sw_frame_lock(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd092, 0x0002, 1, wr_val)
#define rd_cl93n72_tx_dp_ln_clk_en()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd093, 13, 15, __ERR)
#define wr_cl93n72_tx_dp_ln_clk_en(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0004, 2, wr_val)
#define rd_cl93n72_dis_max_wait_timer()               _falcon_tsc_pmd_rde_field_byte(pa, 0xd093, 14, 15, __ERR)
#define wr_cl93n72_dis_max_wait_timer(wr_val)         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0002, 1, wr_val)
#define rd_cl93n72_brk_ring_osc()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd093, 15, 15, __ERR)
#define wr_cl93n72_brk_ring_osc(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd093, 0x0001, 0, wr_val)
#define rd_cl93n72_txfir_post()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd094, 2, 10, __ERR)
#define wr_cl93n72_txfir_post(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd094, 0x3f00, 8, wr_val)
#define rd_cl93n72_txfir_pre()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd094, 11, 11, __ERR)
#define wr_cl93n72_txfir_pre(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd094, 0x001f, 0, wr_val)
#define rd_cl93n72_txfir_main()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd095, 9, 9, __ERR)
#define wr_cl93n72_txfir_main(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd095, 0x007f, 0, wr_val)
#define rd_cl93n72_training_fsm_signal_detect()       _falcon_tsc_pmd_rde_field_byte(pa, 0xd096, 14, 15, __ERR)
#define rd_cl93n72_local_rx_ready()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd096, 15, 15, __ERR)
#define rd_cl93n72_prbs_seed_sel()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd097, 0, 14, __ERR)
#define wr_cl93n72_prbs_seed_sel(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd097, 0xc000, 14, wr_val)
#define rd_cl93n72_prbs_mode_sel()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd097, 2, 15, __ERR)
#define wr_cl93n72_prbs_mode_sel(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd097, 0x2000, 13, wr_val)
#define rd_cl93n72_cl93prbs_poly_sel()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd097, 3, 14, __ERR)
#define wr_cl93n72_cl93prbs_poly_sel(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd097, 0x1800, 11, wr_val)
#define rd_cl93n72_prbs_seed_val()                    _falcon_tsc_pmd_rde_field(pa, 0xd097, 5, 5, __ERR)
#define wr_cl93n72_prbs_seed_val(wr_val)              falcon_tsc_pmd_mwr_reg(pa, 0xd097, 0x07ff, 0, wr_val)
#define rdc_revid_rev_letter()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd100, 0, 14, __ERR)
#define rdc_revid_rev_number()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd100, 2, 13, __ERR)
#define rdc_revid_bonding()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd100, 5, 14, __ERR)
#define rdc_revid_process()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd100, 7, 13, __ERR)
#define rdc_revid_model()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd100, 10, 10, __ERR)
#define rdc_revid_multiplicity()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd10a, 0, 12, __ERR)
#define rdc_revid_mdio()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd10a, 10, 15, __ERR)
#define rdc_revid_micro()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd10a, 11, 15, __ERR)
#define rdc_revid_cl72()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd10a, 12, 15, __ERR)
#define rdc_revid_pir()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd10a, 13, 15, __ERR)
#define rdc_revid_llp()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd10a, 14, 15, __ERR)
#define rdc_revid_eee()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd10a, 15, 15, __ERR)
#define rdc_revid2()                                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd10e, 12, 12, __ERR)
#define rdc_core_s_rstb()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd101, 15, 15, __ERR)
#define wrc_core_s_rstb(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd101, 0x0001, 0, wr_val)
#define rdc_tx_pi_loop_filter_stable()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 1, 15, __ERR)
#define wrc_tx_pi_loop_filter_stable(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x4000, 14, wr_val)
#define rdc_afe_s_pll_reset_frc()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 2, 15, __ERR)
#define wrc_afe_s_pll_reset_frc(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x2000, 13, wr_val)
#define rdc_afe_s_pll_reset_frc_val()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 3, 15, __ERR)
#define wrc_afe_s_pll_reset_frc_val(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x1000, 12, wr_val)
#define rdc_tx_s_clkgate_frc_on()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 4, 15, __ERR)
#define wrc_tx_s_clkgate_frc_on(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0800, 11, wr_val)
#define rdc_tx_s_comclk_frc_on()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 5, 15, __ERR)
#define wrc_tx_s_comclk_frc_on(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0400, 10, wr_val)
#define rdc_tx_s_comclk_sel()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 6, 15, __ERR)
#define wrc_tx_s_comclk_sel(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0200, 9, wr_val)
#define rdc_pmd_tx_clk_vld_frc_val()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 7, 15, __ERR)
#define wrc_pmd_tx_clk_vld_frc_val(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0100, 8, wr_val)
#define rdc_pmd_tx_clk_vld_frc()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 8, 15, __ERR)
#define wrc_pmd_tx_clk_vld_frc(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0080, 7, wr_val)
#define rdc_pmd_mdio_trans_pkill()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 10, 15, __ERR)
#define wrc_pmd_mdio_trans_pkill(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0020, 5, wr_val)
#define rdc_sup_rst_seq_frc()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 11, 15, __ERR)
#define wrc_sup_rst_seq_frc(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0010, 4, wr_val)
#define rdc_sup_rst_seq_frc_val()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 12, 15, __ERR)
#define wrc_sup_rst_seq_frc_val(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0008, 3, wr_val)
#define rdc_pmd_core_dp_h_rstb_pkill()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd102, 14, 15, __ERR)
#define wrc_pmd_core_dp_h_rstb_pkill(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd102, 0x0002, 1, wr_val)
#define rdc_core_multicast_mask_control()             _falcon_tsc_pmd_rde_field_byte(pa, 0xd103, 12, 12, __ERR)
#define wrc_core_multicast_mask_control(wr_val)       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd103, 0x000f, 0, wr_val)
#define rdc_uc_active()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd104, 0, 15, __ERR)
#define wrc_uc_active(wr_val)                         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd104, 0x8000, 15, wr_val)
#define rdc_afe_s_pll_pwrdn()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd104, 1, 15, __ERR)
#define wrc_afe_s_pll_pwrdn(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd104, 0x4000, 14, wr_val)
#define rdc_core_dp_s_rstb()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd104, 2, 15, __ERR)
#define wrc_core_dp_s_rstb(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd104, 0x2000, 13, wr_val)
#define rdc_heartbeat_count_1us()                     _falcon_tsc_pmd_rde_field(pa, 0xd104, 6, 6, __ERR)
#define wrc_heartbeat_count_1us(wr_val)               falcon_tsc_pmd_mwr_reg(pa, 0xd104, 0x03ff, 0, wr_val)
#define rdc_uc_ack_core_dp_reset()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd105, 14, 15, __ERR)
#define wrc_uc_ack_core_dp_reset(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd105, 0x0002, 1, wr_val)
#define rdc_uc_ack_core_cfg_done()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd105, 15, 15, __ERR)
#define wrc_uc_ack_core_cfg_done(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd105, 0x0001, 0, wr_val)
#define rdc_lane_reset_released()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd108, 1, 15, __ERR)
#define rdc_lane_reset_released_index()               _falcon_tsc_pmd_rde_field_byte(pa, 0xd108, 3, 11, __ERR)
#define rdc_core_dp_reset_state()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd108, 13, 13, __ERR)
#define rdc_core_reg_reset_occurred()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd106, 15, 15, __ERR)
#define wrc_core_reg_reset_occurred(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd106, 0x0001, 0, wr_val)
#define rdc_rst_seq_dis_flt_mode()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd107, 0, 14, __ERR)
#define wrc_rst_seq_dis_flt_mode(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd107, 0xc000, 14, wr_val)
#define rdc_pwrdn_seq_timer()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd107, 5, 13, __ERR)
#define wrc_pwrdn_seq_timer(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd107, 0x0700, 8, wr_val)
#define rdc_rst_seq_timer()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd107, 13, 13, __ERR)
#define wrc_rst_seq_timer(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd107, 0x0007, 0, wr_val)
#define rdc_pmd_core_mode()                           _falcon_tsc_pmd_rde_reg(pa, 0xd109, __ERR)
#define rdc_tx_lane_map_2()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd10b, 1, 11, __ERR)
#define wrc_tx_lane_map_2(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd10b, 0x7c00, 10, wr_val)
#define rdc_tx_lane_map_1()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd10b, 6, 11, __ERR)
#define wrc_tx_lane_map_1(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd10b, 0x03e0, 5, wr_val)
#define rdc_tx_lane_map_0()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd10b, 11, 11, __ERR)
#define wrc_tx_lane_map_0(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd10b, 0x001f, 0, wr_val)
#define rdc_lane_addr_1()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd10c, 1, 11, __ERR)
#define wrc_lane_addr_1(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd10c, 0x7c00, 10, wr_val)
#define rdc_lane_addr_0()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd10c, 6, 11, __ERR)
#define wrc_lane_addr_0(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd10c, 0x03e0, 5, wr_val)
#define rdc_tx_lane_map_3()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd10c, 11, 11, __ERR)
#define wrc_tx_lane_map_3(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd10c, 0x001f, 0, wr_val)
#define rdc_lane_addr_3()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd10d, 3, 11, __ERR)
#define wrc_lane_addr_3(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd10d, 0x1f00, 8, wr_val)
#define rdc_lane_addr_2()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd10d, 11, 11, __ERR)
#define wrc_lane_addr_2(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd10d, 0x001f, 0, wr_val)
#define rd_uc_dsc_supp_info()                         _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd03d, 0, 8, __ERR)
#define wr_uc_dsc_supp_info(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd03d, 0xff00, 8, wr_val)
#define rd_uc_dsc_ready_for_cmd()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd03d, 8, 15, __ERR)
#define wr_uc_dsc_ready_for_cmd(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd03d, 0x0080, 7, wr_val)
#define rd_uc_dsc_error_found()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd03d, 9, 15, __ERR)
#define wr_uc_dsc_error_found(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd03d, 0x0040, 6, wr_val)
#define rd_uc_dsc_gp_uc_req()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd03d, 10, 10, __ERR)
#define wr_uc_dsc_gp_uc_req(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd03d, 0x003f, 0, wr_val)
#define rd_uc_dsc_data()                              _falcon_tsc_pmd_rde_reg(pa, 0xd03e, __ERR)
#define wr_uc_dsc_data(wr_val)                        falcon_tsc_pmd_wr_reg(pa, 0xd03e, wr_val)
#define rd_rx_pf_ctrl()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd000, 1, 12, __ERR)
#define wr_rx_pf_ctrl(wr_val)                         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd000, 0x7800, 11, wr_val)
#define rd_rx_pf2_ctrl()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd000, 5, 13, __ERR)
#define wr_rx_pf2_ctrl(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd000, 0x0700, 8, wr_val)
#define rd_rxa_slicer_offset_adj_dn()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd001, 2, 10, __ERR)
#define wr_rxa_slicer_offset_adj_dn(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x3f00, 8, wr_val)
#define rd_rxa_slicer_offset_adj_dp()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd001, 10, 10, __ERR)
#define wr_rxa_slicer_offset_adj_dp(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd001, 0x003f, 0, wr_val)
#define rd_rxa_slicer_offset_adj_zn()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd002, 2, 10, __ERR)
#define wr_rxa_slicer_offset_adj_zn(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd002, 0x3f00, 8, wr_val)
#define rd_rxa_slicer_offset_adj_zp()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd002, 10, 10, __ERR)
#define wr_rxa_slicer_offset_adj_zp(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd002, 0x003f, 0, wr_val)
#define rd_rxa_slicer_offset_adj_lms()                _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd003, 2, 10, __ERR)
#define wr_rxa_slicer_offset_adj_lms(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd003, 0x3f00, 8, wr_val)
#define rd_rxb_slicer_offset_adj_lms()                _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd003, 10, 10, __ERR)
#define wr_rxb_slicer_offset_adj_lms(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd003, 0x003f, 0, wr_val)
#define rd_rxb_slicer_offset_adj_dn()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd004, 2, 10, __ERR)
#define wr_rxb_slicer_offset_adj_dn(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd004, 0x3f00, 8, wr_val)
#define rd_rxb_slicer_offset_adj_dp()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd004, 10, 10, __ERR)
#define wr_rxb_slicer_offset_adj_dp(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd004, 0x003f, 0, wr_val)
#define rd_rxb_slicer_offset_adj_zn()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd005, 2, 10, __ERR)
#define wr_rxb_slicer_offset_adj_zn(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd005, 0x3f00, 8, wr_val)
#define rd_rxb_slicer_offset_adj_zp()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd005, 10, 10, __ERR)
#define wr_rxb_slicer_offset_adj_zp(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd005, 0x003f, 0, wr_val)
#define rd_rxc_slicer_offset_adj_dn()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd006, 2, 10, __ERR)
#define wr_rxc_slicer_offset_adj_dn(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd006, 0x3f00, 8, wr_val)
#define rd_rxc_slicer_offset_adj_dp()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd006, 10, 10, __ERR)
#define wr_rxc_slicer_offset_adj_dp(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd006, 0x003f, 0, wr_val)
#define rd_rxc_slicer_offset_adj_zn()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd007, 2, 10, __ERR)
#define wr_rxc_slicer_offset_adj_zn(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd007, 0x3f00, 8, wr_val)
#define rd_rxc_slicer_offset_adj_zp()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd007, 10, 10, __ERR)
#define wr_rxc_slicer_offset_adj_zp(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd007, 0x003f, 0, wr_val)
#define rd_rxc_slicer_offset_adj_lms()                _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd008, 2, 10, __ERR)
#define wr_rxc_slicer_offset_adj_lms(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd008, 0x3f00, 8, wr_val)
#define rd_rxd_slicer_offset_adj_lms()                _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd008, 10, 10, __ERR)
#define wr_rxd_slicer_offset_adj_lms(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd008, 0x003f, 0, wr_val)
#define rd_rxd_slicer_offset_adj_dn()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd009, 2, 10, __ERR)
#define wr_rxd_slicer_offset_adj_dn(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd009, 0x3f00, 8, wr_val)
#define rd_rxd_slicer_offset_adj_dp()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd009, 10, 10, __ERR)
#define wr_rxd_slicer_offset_adj_dp(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd009, 0x003f, 0, wr_val)
#define rd_rxd_slicer_offset_adj_zn()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd00a, 2, 10, __ERR)
#define wr_rxd_slicer_offset_adj_zn(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd00a, 0x3f00, 8, wr_val)
#define rd_rxd_slicer_offset_adj_zp()                 _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd00a, 10, 10, __ERR)
#define wr_rxd_slicer_offset_adj_zp(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd00a, 0x003f, 0, wr_val)
#define rd_rx_phase_thresh_sel()                      _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd00b, 1, 9, __ERR)
#define wr_rx_phase_thresh_sel(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd00b, 0x7f00, 8, wr_val)
#define rd_rx_lms_thresh_sel()                        _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd00b, 8, 8, __ERR)
#define wr_rx_lms_thresh_sel(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd00b, 0x00ff, 0, wr_val)
#define rd_rxa_dfe_tap2()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd010, 3, 11, __ERR)
#define wr_rxa_dfe_tap2(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x1f00, 8, wr_val)
#define rd_rxb_dfe_tap2()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd010, 11, 11, __ERR)
#define wr_rxb_dfe_tap2(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd010, 0x001f, 0, wr_val)
#define rd_rxc_dfe_tap2()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd011, 3, 11, __ERR)
#define wr_rxc_dfe_tap2(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x1f00, 8, wr_val)
#define rd_rxd_dfe_tap2()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd011, 11, 11, __ERR)
#define wr_rxd_dfe_tap2(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd011, 0x001f, 0, wr_val)
#define rd_rxa_dfe_tap3()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd012, 3, 11, __ERR)
#define wr_rxa_dfe_tap3(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd012, 0x1f00, 8, wr_val)
#define rd_rxb_dfe_tap3()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd012, 11, 11, __ERR)
#define wr_rxb_dfe_tap3(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd012, 0x001f, 0, wr_val)
#define rd_rxc_dfe_tap3()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd013, 3, 11, __ERR)
#define wr_rxc_dfe_tap3(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd013, 0x1f00, 8, wr_val)
#define rd_rxd_dfe_tap3()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd013, 11, 11, __ERR)
#define wr_rxd_dfe_tap3(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd013, 0x001f, 0, wr_val)
#define rd_rxa_dfe_tap4()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd014, 0, 12, __ERR)
#define wr_rxa_dfe_tap4(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd014, 0xf000, 12, wr_val)
#define rd_rxb_dfe_tap4()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd014, 4, 12, __ERR)
#define wr_rxb_dfe_tap4(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd014, 0x0f00, 8, wr_val)
#define rd_rxc_dfe_tap4()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd014, 8, 12, __ERR)
#define wr_rxc_dfe_tap4(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd014, 0x00f0, 4, wr_val)
#define rd_rxd_dfe_tap4()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd014, 12, 12, __ERR)
#define wr_rxd_dfe_tap4(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd014, 0x000f, 0, wr_val)
#define rd_rxa_dfe_tap5()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd015, 0, 12, __ERR)
#define wr_rxa_dfe_tap5(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd015, 0xf000, 12, wr_val)
#define rd_rxb_dfe_tap5()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd015, 4, 12, __ERR)
#define wr_rxb_dfe_tap5(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd015, 0x0f00, 8, wr_val)
#define rd_rxc_dfe_tap5()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd015, 8, 12, __ERR)
#define wr_rxc_dfe_tap5(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd015, 0x00f0, 4, wr_val)
#define rd_rxd_dfe_tap5()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd015, 12, 12, __ERR)
#define wr_rxd_dfe_tap5(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd015, 0x000f, 0, wr_val)
#define rd_rxa_dfe_tap6()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd016, 0, 12, __ERR)
#define wr_rxa_dfe_tap6(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd016, 0xf000, 12, wr_val)
#define rd_rxb_dfe_tap6()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd016, 4, 12, __ERR)
#define wr_rxb_dfe_tap6(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd016, 0x0f00, 8, wr_val)
#define rd_rxc_dfe_tap6()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd016, 8, 12, __ERR)
#define wr_rxc_dfe_tap6(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd016, 0x00f0, 4, wr_val)
#define rd_rxd_dfe_tap6()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd016, 12, 12, __ERR)
#define wr_rxd_dfe_tap6(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd016, 0x000f, 0, wr_val)
#define rd_rxa_dfe_tap7()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd017, 0, 12, __ERR)
#define wr_rxa_dfe_tap7(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0xf000, 12, wr_val)
#define rd_rxb_dfe_tap7()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd017, 4, 12, __ERR)
#define wr_rxb_dfe_tap7(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0x0f00, 8, wr_val)
#define rd_rxc_dfe_tap7()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd017, 8, 12, __ERR)
#define wr_rxc_dfe_tap7(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0x00f0, 4, wr_val)
#define rd_rxd_dfe_tap7()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd017, 12, 12, __ERR)
#define wr_rxd_dfe_tap7(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd017, 0x000f, 0, wr_val)
#define rd_rxa_dfe_tap8()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd018, 0, 12, __ERR)
#define wr_rxa_dfe_tap8(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0xf000, 12, wr_val)
#define rd_rxb_dfe_tap8()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd018, 4, 12, __ERR)
#define wr_rxb_dfe_tap8(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0x0f00, 8, wr_val)
#define rd_rxc_dfe_tap8()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd018, 8, 12, __ERR)
#define wr_rxc_dfe_tap8(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0x00f0, 4, wr_val)
#define rd_rxd_dfe_tap8()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd018, 12, 12, __ERR)
#define wr_rxd_dfe_tap8(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd018, 0x000f, 0, wr_val)
#define rd_rxa_dfe_tap9()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd019, 0, 12, __ERR)
#define wr_rxa_dfe_tap9(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd019, 0xf000, 12, wr_val)
#define rd_rxb_dfe_tap9()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd019, 4, 12, __ERR)
#define wr_rxb_dfe_tap9(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd019, 0x0f00, 8, wr_val)
#define rd_rxc_dfe_tap9()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd019, 8, 12, __ERR)
#define wr_rxc_dfe_tap9(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd019, 0x00f0, 4, wr_val)
#define rd_rxd_dfe_tap9()                             _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd019, 12, 12, __ERR)
#define wr_rxd_dfe_tap9(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd019, 0x000f, 0, wr_val)
#define rd_rxa_dfe_tap10()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd020, 0, 12, __ERR)
#define wr_rxa_dfe_tap10(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd020, 0xf000, 12, wr_val)
#define rd_rxb_dfe_tap10()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd020, 4, 12, __ERR)
#define wr_rxb_dfe_tap10(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd020, 0x0f00, 8, wr_val)
#define rd_rxc_dfe_tap10()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd020, 8, 12, __ERR)
#define wr_rxc_dfe_tap10(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd020, 0x00f0, 4, wr_val)
#define rd_rxd_dfe_tap10()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd020, 12, 12, __ERR)
#define wr_rxd_dfe_tap10(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd020, 0x000f, 0, wr_val)
#define rd_rxa_dfe_tap11()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd021, 0, 12, __ERR)
#define wr_rxa_dfe_tap11(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0xf000, 12, wr_val)
#define rd_rxb_dfe_tap11()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd021, 4, 12, __ERR)
#define wr_rxb_dfe_tap11(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x0f00, 8, wr_val)
#define rd_rxc_dfe_tap11()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd021, 8, 12, __ERR)
#define wr_rxc_dfe_tap11(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x00f0, 4, wr_val)
#define rd_rxd_dfe_tap11()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd021, 12, 12, __ERR)
#define wr_rxd_dfe_tap11(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd021, 0x000f, 0, wr_val)
#define rd_rxa_dfe_tap12()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd022, 0, 12, __ERR)
#define wr_rxa_dfe_tap12(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd022, 0xf000, 12, wr_val)
#define rd_rxb_dfe_tap12()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd022, 4, 12, __ERR)
#define wr_rxb_dfe_tap12(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd022, 0x0f00, 8, wr_val)
#define rd_rxc_dfe_tap12()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd022, 8, 12, __ERR)
#define wr_rxc_dfe_tap12(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd022, 0x00f0, 4, wr_val)
#define rd_rxd_dfe_tap12()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd022, 12, 12, __ERR)
#define wr_rxd_dfe_tap12(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd022, 0x000f, 0, wr_val)
#define rd_rxa_dfe_tap13()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd023, 0, 12, __ERR)
#define wr_rxa_dfe_tap13(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0xf000, 12, wr_val)
#define rd_rxb_dfe_tap13()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd023, 4, 12, __ERR)
#define wr_rxb_dfe_tap13(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x0f00, 8, wr_val)
#define rd_rxc_dfe_tap13()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd023, 8, 12, __ERR)
#define wr_rxc_dfe_tap13(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x00f0, 4, wr_val)
#define rd_rxd_dfe_tap13()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd023, 12, 12, __ERR)
#define wr_rxd_dfe_tap13(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd023, 0x000f, 0, wr_val)
#define rd_rxa_dfe_tap14()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd024, 0, 12, __ERR)
#define wr_rxa_dfe_tap14(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd024, 0xf000, 12, wr_val)
#define rd_rxb_dfe_tap14()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd024, 4, 12, __ERR)
#define wr_rxb_dfe_tap14(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd024, 0x0f00, 8, wr_val)
#define rd_rxc_dfe_tap14()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd024, 8, 12, __ERR)
#define wr_rxc_dfe_tap14(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd024, 0x00f0, 4, wr_val)
#define rd_rxd_dfe_tap14()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd024, 12, 12, __ERR)
#define wr_rxd_dfe_tap14(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd024, 0x000f, 0, wr_val)
#define rd_rxa_dfe_tap7_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd025, 0, 14, __ERR)
#define wr_rxa_dfe_tap7_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0xc000, 14, wr_val)
#define rd_rxa_dfe_tap8_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd025, 2, 14, __ERR)
#define wr_rxa_dfe_tap8_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x3000, 12, wr_val)
#define rd_rxb_dfe_tap7_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd025, 4, 14, __ERR)
#define wr_rxb_dfe_tap7_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0c00, 10, wr_val)
#define rd_rxb_dfe_tap8_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd025, 6, 14, __ERR)
#define wr_rxb_dfe_tap8_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0300, 8, wr_val)
#define rd_rxc_dfe_tap7_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd025, 8, 14, __ERR)
#define wr_rxc_dfe_tap7_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x00c0, 6, wr_val)
#define rd_rxc_dfe_tap8_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd025, 10, 14, __ERR)
#define wr_rxc_dfe_tap8_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0030, 4, wr_val)
#define rd_rxd_dfe_tap7_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd025, 12, 14, __ERR)
#define wr_rxd_dfe_tap7_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x000c, 2, wr_val)
#define rd_rxd_dfe_tap8_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd025, 14, 14, __ERR)
#define wr_rxd_dfe_tap8_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd025, 0x0003, 0, wr_val)
#define rd_rxa_dfe_tap9_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd026, 0, 14, __ERR)
#define wr_rxa_dfe_tap9_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0xc000, 14, wr_val)
#define rd_rxa_dfe_tap10_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd026, 2, 14, __ERR)
#define wr_rxa_dfe_tap10_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x3000, 12, wr_val)
#define rd_rxb_dfe_tap9_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd026, 4, 14, __ERR)
#define wr_rxb_dfe_tap9_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x0c00, 10, wr_val)
#define rd_rxb_dfe_tap10_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd026, 6, 14, __ERR)
#define wr_rxb_dfe_tap10_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x0300, 8, wr_val)
#define rd_rxc_dfe_tap9_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd026, 8, 14, __ERR)
#define wr_rxc_dfe_tap9_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x00c0, 6, wr_val)
#define rd_rxc_dfe_tap10_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd026, 10, 14, __ERR)
#define wr_rxc_dfe_tap10_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x0030, 4, wr_val)
#define rd_rxd_dfe_tap9_mux()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd026, 12, 14, __ERR)
#define wr_rxd_dfe_tap9_mux(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x000c, 2, wr_val)
#define rd_rxd_dfe_tap10_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd026, 14, 14, __ERR)
#define wr_rxd_dfe_tap10_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd026, 0x0003, 0, wr_val)
#define rd_rxa_dfe_tap11_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd027, 0, 14, __ERR)
#define wr_rxa_dfe_tap11_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0xc000, 14, wr_val)
#define rd_rxa_dfe_tap12_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd027, 2, 14, __ERR)
#define wr_rxa_dfe_tap12_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x3000, 12, wr_val)
#define rd_rxb_dfe_tap11_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd027, 4, 14, __ERR)
#define wr_rxb_dfe_tap11_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0c00, 10, wr_val)
#define rd_rxb_dfe_tap12_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd027, 6, 14, __ERR)
#define wr_rxb_dfe_tap12_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0300, 8, wr_val)
#define rd_rxc_dfe_tap11_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd027, 8, 14, __ERR)
#define wr_rxc_dfe_tap11_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x00c0, 6, wr_val)
#define rd_rxc_dfe_tap12_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd027, 10, 14, __ERR)
#define wr_rxc_dfe_tap12_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0030, 4, wr_val)
#define rd_rxd_dfe_tap11_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd027, 12, 14, __ERR)
#define wr_rxd_dfe_tap11_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x000c, 2, wr_val)
#define rd_rxd_dfe_tap12_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd027, 14, 14, __ERR)
#define wr_rxd_dfe_tap12_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd027, 0x0003, 0, wr_val)
#define rd_rxa_dfe_tap13_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd028, 0, 14, __ERR)
#define wr_rxa_dfe_tap13_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0xc000, 14, wr_val)
#define rd_rxa_dfe_tap14_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd028, 2, 14, __ERR)
#define wr_rxa_dfe_tap14_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x3000, 12, wr_val)
#define rd_rxb_dfe_tap13_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd028, 4, 14, __ERR)
#define wr_rxb_dfe_tap13_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x0c00, 10, wr_val)
#define rd_rxb_dfe_tap14_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd028, 6, 14, __ERR)
#define wr_rxb_dfe_tap14_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x0300, 8, wr_val)
#define rd_rxc_dfe_tap13_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd028, 8, 14, __ERR)
#define wr_rxc_dfe_tap13_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x00c0, 6, wr_val)
#define rd_rxc_dfe_tap14_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd028, 10, 14, __ERR)
#define wr_rxc_dfe_tap14_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x0030, 4, wr_val)
#define rd_rxd_dfe_tap13_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd028, 12, 14, __ERR)
#define wr_rxd_dfe_tap13_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x000c, 2, wr_val)
#define rd_rxd_dfe_tap14_mux()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd028, 14, 14, __ERR)
#define wr_rxd_dfe_tap14_mux(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd028, 0x0003, 0, wr_val)
#define rd_preset_dsc_afe_bank()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd029, 15, 15, __ERR)
#define wr_preset_dsc_afe_bank(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd029, 0x0001, 0, wr_val)
#define rd_rx_vga_ctrl()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd04d, 1, 9, __ERR)
#define rd_rx_data_thresh_sel()                       _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd04d, 9, 9, __ERR)
#define rd_trnsum_b_low()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd042, 0, 8, __ERR)
#define rd_trnsum_c()                                 _falcon_tsc_pmd_rde_field_signed(pa, 0xd045, 0, 0, __ERR)
#define rd_trnsum_b()                                 _falcon_tsc_pmd_rde_field_signed(pa, 0xd043, 0, 0, __ERR)
#define rd_trnsum_a_low()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd040, 0, 8, __ERR)
#define rd_trnsum_a()                                 _falcon_tsc_pmd_rde_field_signed(pa, 0xd041, 0, 0, __ERR)
#define rd_trnsum_c_low()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd044, 0, 8, __ERR)
#define rd_trnsum_d()                                 _falcon_tsc_pmd_rde_field_signed(pa, 0xd047, 0, 0, __ERR)
#define rd_trnsum_d_low()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd046, 0, 8, __ERR)
#define rd_trnsum_low()                               _falcon_tsc_pmd_rde_field(pa, 0xd048, 0, 6, __ERR)
#define rd_trnsum()                                   _falcon_tsc_pmd_rde_field_signed(pa, 0xd049, 0, 0, __ERR)
#define rd_dc_offset_bin()                            _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd04c, 9, 9, __ERR)
#define rd_rx_pi_manual_strobe()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd053, 4, 15, __ERR)
#define wr_rx_pi_manual_strobe(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd053, 0x0800, 11, wr_val)
#define rd_rx_pi_manual_mode()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd053, 5, 15, __ERR)
#define wr_rx_pi_manual_mode(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd053, 0x0400, 10, wr_val)
#define rd_rx_pi_phase_step_dir()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd053, 6, 15, __ERR)
#define wr_rx_pi_phase_step_dir(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd053, 0x0200, 9, wr_val)
#define rd_rx_pi_phase_step_cnt()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd053, 7, 13, __ERR)
#define wr_rx_pi_phase_step_cnt(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd053, 0x01c0, 6, wr_val)
#define rd_rx_pi_slicers_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd053, 10, 10, __ERR)
#define wr_rx_pi_slicers_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd053, 0x003f, 0, wr_val)
#define rd_trnsum_tap_sign()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd058, 0, 8, __ERR)
#define wr_trnsum_tap_sign(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd058, 0xff00, 8, wr_val)
#define rd_trnsum_tap_en()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd058, 8, 8, __ERR)
#define wr_trnsum_tap_en(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd058, 0x00ff, 0, wr_val)
#define rd_trnsum_inv_pattern_en()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd056, 0, 15, __ERR)
#define wr_trnsum_inv_pattern_en(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd056, 0x8000, 15, wr_val)
#define rd_trnsum_edge_pattern_en()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd056, 1, 15, __ERR)
#define wr_trnsum_edge_pattern_en(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd056, 0x4000, 14, wr_val)
#define rd_trnsum_pattern_full_check_off()            _falcon_tsc_pmd_rde_field_byte(pa, 0xd056, 3, 15, __ERR)
#define wr_trnsum_pattern_full_check_off(wr_val)      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd056, 0x1000, 12, wr_val)
#define rd_trnsum_pattern()                           _falcon_tsc_pmd_rde_field(pa, 0xd056, 6, 6, __ERR)
#define wr_trnsum_pattern(wr_val)                     falcon_tsc_pmd_mwr_reg(pa, 0xd056, 0x03ff, 0, wr_val)
#define rd_trnsum_pattern_bit_en()                    _falcon_tsc_pmd_rde_field(pa, 0xd057, 6, 6, __ERR)
#define wr_trnsum_pattern_bit_en(wr_val)              falcon_tsc_pmd_mwr_reg(pa, 0xd057, 0x03ff, 0, wr_val)
#define rd_trnsum_en()                                _falcon_tsc_pmd_rde_field_byte(pa, 0xd055, 0, 15, __ERR)
#define wr_trnsum_en(wr_val)                          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x8000, 15, wr_val)
#define rd_trnsum_eye_closure_en()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd055, 1, 15, __ERR)
#define wr_trnsum_eye_closure_en(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x4000, 14, wr_val)
#define rd_trnsum_random_tapsel_disable()             _falcon_tsc_pmd_rde_field_byte(pa, 0xd055, 2, 15, __ERR)
#define wr_trnsum_random_tapsel_disable(wr_val)       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x2000, 13, wr_val)
#define rd_trnsum_qphase_mult_en()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd055, 3, 15, __ERR)
#define wr_trnsum_qphase_mult_en(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x1000, 12, wr_val)
#define rd_trnsum_cor_sel()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd055, 6, 14, __ERR)
#define wr_trnsum_cor_sel(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x0300, 8, wr_val)
#define rd_trnsum_tap_range_sel()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd055, 9, 13, __ERR)
#define wr_trnsum_tap_range_sel(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x0070, 4, wr_val)
#define rd_trnsum_sel_emux()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd055, 13, 15, __ERR)
#define wr_trnsum_sel_emux(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x0004, 2, wr_val)
#define rd_trnsum_gain()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd055, 14, 14, __ERR)
#define wr_trnsum_gain(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd055, 0x0003, 0, wr_val)
#define rd_cdr_1g_manual_strobe()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd052, 6, 15, __ERR)
#define wr_cdr_1g_manual_strobe(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0200, 9, wr_val)
#define rd_cdr_1g_manual_mode()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd052, 7, 15, __ERR)
#define wr_cdr_1g_manual_mode(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0100, 8, wr_val)
#define rd_phs_sum_ignore_dsc_lock()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd052, 8, 15, __ERR)
#define wr_phs_sum_ignore_dsc_lock(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0080, 7, wr_val)
#define rd_tx_pi_loop_timing_src_sel()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd052, 9, 15, __ERR)
#define wr_tx_pi_loop_timing_src_sel(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0040, 6, wr_val)
#define rd_cdr_1g_force_en()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd052, 10, 15, __ERR)
#define wr_cdr_1g_force_en(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0020, 5, wr_val)
#define rd_cdr_1g_swap_pz()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd052, 11, 15, __ERR)
#define wr_cdr_1g_swap_pz(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x0010, 4, wr_val)
#define rd_cdr_lm_thr_sel()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd052, 12, 12, __ERR)
#define wr_cdr_lm_thr_sel(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd052, 0x000f, 0, wr_val)
#define rd_cdr_freq_override_val()                    _falcon_tsc_pmd_rde_field_signed(pa, 0xd051, 0, 5, __ERR)
#define wr_cdr_freq_override_val(wr_val)              falcon_tsc_pmd_mwr_reg(pa, 0xd051, 0xffe0, 5, wr_val)
#define rd_cdr_zero_polarity()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd050, 6, 15, __ERR)
#define wr_cdr_zero_polarity(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0200, 9, wr_val)
#define rd_cdr_freq_override_en()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd050, 7, 15, __ERR)
#define wr_cdr_freq_override_en(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0100, 8, wr_val)
#define rd_cdr_integ_sat_sel()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd050, 8, 15, __ERR)
#define wr_cdr_integ_sat_sel(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0080, 7, wr_val)
#define rd_cdr_phase_err_frz()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd050, 9, 15, __ERR)
#define wr_cdr_phase_err_frz(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0040, 6, wr_val)
#define rd_cdr_integ_reg_clr()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd050, 10, 15, __ERR)
#define wr_cdr_integ_reg_clr(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0020, 5, wr_val)
#define rd_cdr_freq_en()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd050, 12, 15, __ERR)
#define wr_cdr_freq_en(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0008, 3, wr_val)
#define rd_os_pattern_enhanced()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd050, 13, 15, __ERR)
#define wr_os_pattern_enhanced(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0004, 2, wr_val)
#define rd_br_pd_en()                                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd050, 14, 15, __ERR)
#define wr_br_pd_en(wr_val)                           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0002, 1, wr_val)
#define rd_os_all_edges()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd050, 15, 15, __ERR)
#define wr_os_all_edges(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd050, 0x0001, 0, wr_val)
#define rd_tdt_cycle_bin()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd059, 0, 12, __ERR)
#define wr_tdt_cycle_bin(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd059, 0xf000, 12, wr_val)
#define rd_tdt_cycle_sel()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd059, 4, 12, __ERR)
#define wr_tdt_cycle_sel(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd059, 0x0f00, 8, wr_val)
#define rd_tdt_trnsum_en()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd059, 8, 15, __ERR)
#define wr_tdt_trnsum_en(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd059, 0x0080, 7, wr_val)
#define rd_tdt_prbs_mode()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd059, 9, 15, __ERR)
#define wr_tdt_prbs_mode(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd059, 0x0040, 6, wr_val)
#define rd_tdt_bit_sel()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd059, 10, 10, __ERR)
#define wr_tdt_bit_sel(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd059, 0x003f, 0, wr_val)
#define rd_cdr_1g_trnsum_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd05a, 14, 15, __ERR)
#define wr_cdr_1g_trnsum_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05a, 0x0002, 1, wr_val)
#define rd_tdt_prbs_slip()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd05a, 15, 15, __ERR)
#define wr_tdt_prbs_slip(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05a, 0x0001, 0, wr_val)
#define rd_vga_write()                                _falcon_tsc_pmd_rde_field_byte(pa, 0xd05c, 0, 15, __ERR)
#define wr_vga_write(wr_val)                          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x8000, 15, wr_val)
#define rd_rx_vga_ctrl_val()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd05c, 1, 9, __ERR)
#define wr_rx_vga_ctrl_val(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x7f00, 8, wr_val)
#define rd_vga_inc()                                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd05c, 8, 15, __ERR)
#define wr_vga_inc(wr_val)                            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x0080, 7, wr_val)
#define rd_vga_dec()                                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd05c, 10, 15, __ERR)
#define wr_vga_dec(wr_val)                            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x0020, 5, wr_val)
#define rd_dc_offs_write_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd05c, 11, 15, __ERR)
#define wr_dc_offs_write_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x0010, 4, wr_val)
#define rd_uc_trnsum_en()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd05c, 12, 15, __ERR)
#define wr_uc_trnsum_en(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x0008, 3, wr_val)
#define rd_vga_timer_t2()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd05c, 13, 13, __ERR)
#define wr_vga_timer_t2(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05c, 0x0007, 0, wr_val)
#define rd_data_thresh_write()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd05d, 0, 15, __ERR)
#define wr_data_thresh_write(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05d, 0x8000, 15, wr_val)
#define rd_data_thresh_sel_val()                      _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd05d, 1, 9, __ERR)
#define wr_data_thresh_sel_val(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05d, 0x7f00, 8, wr_val)
#define rd_thresh_step_size()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd05d, 10, 14, __ERR)
#define wr_thresh_step_size(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05d, 0x0030, 4, wr_val)
#define rd_thresh_timer_t1()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd05d, 14, 14, __ERR)
#define wr_thresh_timer_t1(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05d, 0x0003, 0, wr_val)
#define rd_dc_offs_write_frc_en()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd05e, 0, 15, __ERR)
#define wr_dc_offs_write_frc_en(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x8000, 15, wr_val)
#define rd_dc_offs_write_val()                        _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd05e, 1, 9, __ERR)
#define wr_dc_offs_write_val(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x7f00, 8, wr_val)
#define rd_dc_offs_acc_clr()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd05e, 8, 15, __ERR)
#define wr_dc_offs_acc_clr(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0080, 7, wr_val)
#define rd_dc_offs_gain()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd05e, 9, 14, __ERR)
#define wr_dc_offs_gain(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0060, 5, wr_val)
#define rd_dc_offs_gradient_invert()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd05e, 11, 15, __ERR)
#define wr_dc_offs_gradient_invert(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0010, 4, wr_val)
#define rd_dc_offs_hys_mag()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd05e, 12, 15, __ERR)
#define wr_dc_offs_hys_mag(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0008, 3, wr_val)
#define rd_dc_offs_hys_en()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd05e, 13, 15, __ERR)
#define wr_dc_offs_hys_en(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0004, 2, wr_val)
#define rd_dc_offs_en()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd05e, 15, 15, __ERR)
#define wr_dc_offs_en(wr_val)                         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd05e, 0x0001, 0, wr_val)
#define rd_eee_mode_en()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd060, 14, 15, __ERR)
#define wr_eee_mode_en(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0002, 1, wr_val)
#define rd_eee_quiet_rx_afe_pwrdwn_val()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd060, 13, 15, __ERR)
#define wr_eee_quiet_rx_afe_pwrdwn_val(wr_val)        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0004, 2, wr_val)
#define rd_ignore_rx_mode()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd060, 12, 15, __ERR)
#define wr_ignore_rx_mode(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0008, 3, wr_val)
#define rd_cl72_timer_en()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd060, 11, 15, __ERR)
#define wr_cl72_timer_en(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0010, 4, wr_val)
#define rd_uc_tune_en()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd060, 10, 15, __ERR)
#define wr_uc_tune_en(wr_val)                         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0020, 5, wr_val)
#define rd_hw_tune_en()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd060, 9, 15, __ERR)
#define wr_hw_tune_en(wr_val)                         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0040, 6, wr_val)
#define rd_eee_measure_en()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd060, 7, 15, __ERR)
#define wr_eee_measure_en(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0100, 8, wr_val)
#define rd_uc_ack_dsc_eee_done()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd060, 4, 15, __ERR)
#define wr_uc_ack_dsc_eee_done(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x0800, 11, wr_val)
#define rd_uc_ack_dsc_restart()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd060, 2, 15, __ERR)
#define wr_uc_ack_dsc_restart(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x2000, 13, wr_val)
#define rd_uc_ack_dsc_config()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd060, 1, 15, __ERR)
#define wr_uc_ack_dsc_config(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x4000, 14, wr_val)
#define rd_set_meas_incomplete()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd060, 0, 15, __ERR)
#define wr_set_meas_incomplete(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd060, 0x8000, 15, wr_val)
#define rd_rx_dsc_lock_frc()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 15, 15, __ERR)
#define wr_rx_dsc_lock_frc(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0001, 0, wr_val)
#define rd_rx_dsc_lock_frc_val()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 14, 15, __ERR)
#define wr_rx_dsc_lock_frc_val(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0002, 1, wr_val)
#define rd_dsc_clr_frc()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 13, 15, __ERR)
#define wr_dsc_clr_frc(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0004, 2, wr_val)
#define rd_dsc_clr_frc_val()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 12, 15, __ERR)
#define wr_dsc_clr_frc_val(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0008, 3, wr_val)
#define rd_trnsum_frz_frc()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 11, 15, __ERR)
#define wr_trnsum_frz_frc(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0010, 4, wr_val)
#define rd_trnsum_frz_frc_val()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 10, 15, __ERR)
#define wr_trnsum_frz_frc_val(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0020, 5, wr_val)
#define rd_timer_done_frc()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 9, 15, __ERR)
#define wr_timer_done_frc(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0040, 6, wr_val)
#define rd_timer_done_frc_val()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 8, 15, __ERR)
#define wr_timer_done_frc_val(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0080, 7, wr_val)
#define rd_freq_upd_en_frc()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 7, 15, __ERR)
#define wr_freq_upd_en_frc(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0100, 8, wr_val)
#define rd_freq_upd_en_frc_val()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 6, 15, __ERR)
#define wr_freq_upd_en_frc_val(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0200, 9, wr_val)
#define rd_cdr_frz_frc()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 5, 15, __ERR)
#define wr_cdr_frz_frc(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0400, 10, wr_val)
#define rd_cdr_frz_frc_val()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 4, 15, __ERR)
#define wr_cdr_frz_frc_val(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x0800, 11, wr_val)
#define rd_trnsum_clr_frc()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 3, 15, __ERR)
#define wr_trnsum_clr_frc(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x1000, 12, wr_val)
#define rd_trnsum_clr_frc_val()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd061, 2, 15, __ERR)
#define wr_trnsum_clr_frc_val(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd061, 0x2000, 13, wr_val)
#define rd_eee_lfsr_cnt()                             _falcon_tsc_pmd_rde_field(pa, 0xd062, 3, 3, __ERR)
#define wr_eee_lfsr_cnt(wr_val)                       falcon_tsc_pmd_mwr_reg(pa, 0xd062, 0x1fff, 0, wr_val)
#define rd_measure_lfsr_cnt()                         _falcon_tsc_pmd_rde_field(pa, 0xd063, 3, 3, __ERR)
#define wr_measure_lfsr_cnt(wr_val)                   falcon_tsc_pmd_mwr_reg(pa, 0xd063, 0x1fff, 0, wr_val)
#define rd_acq_cdr_timeout()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd064, 11, 11, __ERR)
#define wr_acq_cdr_timeout(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd064, 0x001f, 0, wr_val)
#define rd_cdr_settle_timeout()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd064, 6, 11, __ERR)
#define wr_cdr_settle_timeout(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd064, 0x03e0, 5, wr_val)
#define rd_hw_tune_timeout()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd064, 1, 11, __ERR)
#define wr_hw_tune_timeout(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd064, 0x7c00, 10, wr_val)
#define rd_measure_timeout()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd065, 11, 11, __ERR)
#define wr_measure_timeout(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd065, 0x001f, 0, wr_val)
#define rd_eee_acq_cdr_timeout()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd065, 6, 11, __ERR)
#define wr_eee_acq_cdr_timeout(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd065, 0x03e0, 5, wr_val)
#define rd_eee_cdr_settle_timeout()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd065, 1, 11, __ERR)
#define wr_eee_cdr_settle_timeout(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd065, 0x7c00, 10, wr_val)
#define rd_eee_hw_tune_timeout()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd066, 11, 11, __ERR)
#define wr_eee_hw_tune_timeout(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd066, 0x001f, 0, wr_val)
#define rd_eee_ana_pwr_timeout()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd066, 1, 11, __ERR)
#define wr_eee_ana_pwr_timeout(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd066, 0x7c00, 10, wr_val)
#define rd_cdr_bwsel_integ_acqcdr()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd067, 12, 12, __ERR)
#define wr_cdr_bwsel_integ_acqcdr(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd067, 0x000f, 0, wr_val)
#define rd_cdr_bwsel_integ_eee_acqcdr()               _falcon_tsc_pmd_rde_field_byte(pa, 0xd067, 8, 12, __ERR)
#define wr_cdr_bwsel_integ_eee_acqcdr(wr_val)         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd067, 0x00f0, 4, wr_val)
#define rd_cdr_bwsel_integ_norm()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd067, 4, 12, __ERR)
#define wr_cdr_bwsel_integ_norm(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd067, 0x0f00, 8, wr_val)
#define rd_cdr_bwsel_prop_acqcdr()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd067, 3, 15, __ERR)
#define wr_cdr_bwsel_prop_acqcdr(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd067, 0x1000, 12, wr_val)
#define rd_cdr_bwsel_prop_norm()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd067, 1, 15, __ERR)
#define wr_cdr_bwsel_prop_norm(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd067, 0x4000, 14, wr_val)
#define rd_phase_err_offset()                         _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd068, 12, 12, __ERR)
#define wr_phase_err_offset(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x000f, 0, wr_val)
#define rd_eee_phase_err_offset()                     _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd068, 8, 12, __ERR)
#define wr_eee_phase_err_offset(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x00f0, 4, wr_val)
#define rd_phase_err_offset_en()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd068, 6, 14, __ERR)
#define wr_phase_err_offset_en(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x0300, 8, wr_val)
#define rd_eee_phase_err_offset_en()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd068, 4, 14, __ERR)
#define wr_eee_phase_err_offset_en(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x0c00, 10, wr_val)
#define rd_cdr_bwsel_prop_eee_acqcdr()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd068, 1, 15, __ERR)
#define wr_cdr_bwsel_prop_eee_acqcdr(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd068, 0x4000, 14, wr_val)
#define rd_rx_restart_pmd()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd069, 15, 15, __ERR)
#define wr_rx_restart_pmd(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd069, 0x0001, 0, wr_val)
#define rd_rx_restart_pmd_hold()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd069, 14, 15, __ERR)
#define wr_rx_restart_pmd_hold(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd069, 0x0002, 1, wr_val)
#define rd_dsc_state_one_hot()                        _falcon_tsc_pmd_rde_field(pa, 0xd06b, 6, 6, __ERR)
#define rd_dsc_state_eee_one_hot()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd06c, 9, 9, __ERR)
#define rd_restart_pi_ext_mode()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd06d, 15, 15, __ERR)
#define rd_restart_sigdet()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd06d, 14, 15, __ERR)
#define rd_restart_pmd_restart()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd06d, 13, 15, __ERR)
#define rd_eee_quiet_from_eee_states()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd06d, 12, 15, __ERR)
#define rd_dsc_state()                                _falcon_tsc_pmd_rde_field_byte(pa, 0xd06e, 0, 11, __ERR)
#define rd_dsc_sm_gp_uc_req()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd06e, 5, 10, __ERR)
#define rd_dsc_sm_ready_for_cmd()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd06e, 11, 15, __ERR)
#define rd_dsc_sm_scratch()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd06e, 12, 12, __ERR)
#define rd_eee_measure_cnt()                          _falcon_tsc_pmd_rde_field(pa, 0xd06a, 0, 7, __ERR)
#define rd_meas_incomplete()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd06a, 14, 15, __ERR)
#define rd_rx_dsc_lock()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd06a, 15, 15, __ERR)
#define rd_rx_pi_cnt_bin_pq()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd076, 0, 8, __ERR)
#define rd_rx_pi_cnt_bin_p()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd076, 8, 8, __ERR)
#define rd_cdr_vco_reg()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd074, 0, 12, __ERR)
#define rd_cdr_phase_error()                          _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd074, 10, 10, __ERR)
#define rd_rx_pi_cnt_bin_lq()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd077, 0, 8, __ERR)
#define rd_rx_pi_cnt_bin_l()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd077, 8, 8, __ERR)
#define rd_rx_pi_cnt_bin_dq()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd075, 0, 8, __ERR)
#define rd_rx_pi_cnt_bin_d()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd075, 8, 8, __ERR)
#define rd_rx_pi_cnt_bin_d_ld()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd071, 0, 8, __ERR)
#define rd_rx_pi_cnt_bin_l_ld()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd071, 8, 8, __ERR)
#define rd_rx_pi_cnt_bin_d_pd()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd070, 0, 8, __ERR)
#define rd_rx_pi_cnt_bin_p_pd()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd070, 8, 8, __ERR)
#define rd_rx_data_15_to_0()                          _falcon_tsc_pmd_rde_reg(pa, 0xd072, __ERR)
#define rd_rx_data_35_to_20()                         _falcon_tsc_pmd_rde_reg(pa, 0xd073, __ERR)
#define rd_cdr_integ_reg()                            _falcon_tsc_pmd_rde_field_signed(pa, 0xd078, 0, 0, __ERR)
#define rd_cdr_1g_phase_pointer()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd07a, 8, 8, __ERR)
#define rd_cdr_lm_outoflock()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd079, 15, 15, __ERR)
#define rd_preset_dsc_a_bank()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd07e, 13, 15, __ERR)
#define wr_preset_dsc_a_bank(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd07e, 0x0004, 2, wr_val)
#define rd_preset_dsc_d_bank()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd07e, 14, 15, __ERR)
#define wr_preset_dsc_d_bank(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd07e, 0x0002, 1, wr_val)
#define rd_preset_dsc_c_bank()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd07e, 15, 15, __ERR)
#define wr_preset_dsc_c_bank(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd07e, 0x0001, 0, wr_val)
#define rdc_mdio_blk_addr()                           _falcon_tsc_pmd_rde_field(pa, 0xffdf, 1, 5, __ERR)
#define wrc_mdio_blk_addr(wr_val)                     falcon_tsc_pmd_mwr_reg(pa, 0xffdf, 0x7ff0, 4, wr_val)
#define rdc_mdio_function()                           _falcon_tsc_pmd_rde_field_byte(pa, 0x000d, 0, 14, __ERR)
#define wrc_mdio_function(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0x000d, 0xc000, 14, wr_val)
#define rdc_mdio_devad()                              _falcon_tsc_pmd_rde_field_byte(pa, 0x000d, 11, 11, __ERR)
#define wrc_mdio_devad(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0x000d, 0x001f, 0, wr_val)
#define rdc_mdio_addr_data()                          _falcon_tsc_pmd_rde_reg(pa, 0x000e, __ERR)
#define wrc_mdio_addr_data(wr_val)                    falcon_tsc_pmd_wr_reg(pa, 0x000e, wr_val)
#define rdc_mdio_maskdata()                           _falcon_tsc_pmd_rde_reg(pa, 0xffdb, __ERR)
#define wrc_mdio_maskdata(wr_val)                     falcon_tsc_pmd_wr_reg(pa, 0xffdb, wr_val)
#define rdc_mdio_brcst_port_addr()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xffdc, 11, 11, __ERR)
#define wrc_mdio_brcst_port_addr(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xffdc, 0x001f, 0, wr_val)
#define rdc_mdio_multi_prts_en()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xffdd, 0, 15, __ERR)
#define wrc_mdio_multi_prts_en(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x8000, 15, wr_val)
#define rdc_mdio_multi_mmds_en()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xffdd, 1, 15, __ERR)
#define wrc_mdio_multi_mmds_en(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x4000, 14, wr_val)
#define rdc_mdio_dev_pcs_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xffdd, 9, 15, __ERR)
#define wrc_mdio_dev_pcs_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0040, 6, wr_val)
#define rdc_mdio_dev_dte_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xffdd, 10, 15, __ERR)
#define wrc_mdio_dev_dte_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0020, 5, wr_val)
#define rdc_mdio_dev_phy_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xffdd, 11, 15, __ERR)
#define wrc_mdio_dev_phy_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0010, 4, wr_val)
#define rdc_mdio_dev_an_en()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xffdd, 12, 15, __ERR)
#define wrc_mdio_dev_an_en(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0008, 3, wr_val)
#define rdc_mdio_dev_pmd_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xffdd, 13, 15, __ERR)
#define wrc_mdio_dev_pmd_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0004, 2, wr_val)
#define rdc_mdio_dev_cl22_en()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xffdd, 15, 15, __ERR)
#define wrc_mdio_dev_cl22_en(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xffdd, 0x0001, 0, wr_val)
#define rdc_mdio_aer()                                _falcon_tsc_pmd_rde_reg(pa, 0xffde, __ERR)
#define wrc_mdio_aer(wr_val)                          falcon_tsc_pmd_wr_reg(pa, 0xffde, wr_val)
#define rdc_micro_core_clk_en()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd200, 14, 15, __ERR)
#define wrc_micro_core_clk_en(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd200, 0x0002, 1, wr_val)
#define rdc_micro_master_clk_en()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd200, 15, 15, __ERR)
#define wrc_micro_master_clk_en(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd200, 0x0001, 0, wr_val)
#define rdc_micro_pram_if_rstb()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd201, 12, 15, __ERR)
#define wrc_micro_pram_if_rstb(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd201, 0x0008, 3, wr_val)
#define rdc_micro_core_rstb()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd201, 14, 15, __ERR)
#define wrc_micro_core_rstb(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd201, 0x0002, 1, wr_val)
#define rdc_micro_master_rstb()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd201, 15, 15, __ERR)
#define wrc_micro_master_rstb(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd201, 0x0001, 0, wr_val)
#define rdc_micro_autoinc_rdaddr_en()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd202, 2, 15, __ERR)
#define wrc_micro_autoinc_rdaddr_en(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x2000, 13, wr_val)
#define rdc_micro_autoinc_wraddr_en()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd202, 3, 15, __ERR)
#define wrc_micro_autoinc_wraddr_en(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x1000, 12, wr_val)
#define rdc_micro_ra_init()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd202, 6, 14, __ERR)
#define wrc_micro_ra_init(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0300, 8, wr_val)
#define rdc_micro_ra_rddatasize()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd202, 10, 14, __ERR)
#define wrc_micro_ra_rddatasize(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0030, 4, wr_val)
#define rdc_micro_ra_wrdatasize()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd202, 14, 14, __ERR)
#define wrc_micro_ra_wrdatasize(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd202, 0x0003, 0, wr_val)
#define rdc_micro_ra_initdone()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd203, 15, 15, __ERR)
#define rdc_micro_ra_wraddr_lsw()                     _falcon_tsc_pmd_rde_reg(pa, 0xd204, __ERR)
#define wrc_micro_ra_wraddr_lsw(wr_val)               falcon_tsc_pmd_wr_reg(pa, 0xd204, wr_val)
#define rdc_micro_ra_wraddr_msw()                     _falcon_tsc_pmd_rde_reg(pa, 0xd205, __ERR)
#define wrc_micro_ra_wraddr_msw(wr_val)               falcon_tsc_pmd_wr_reg(pa, 0xd205, wr_val)
#define rdc_micro_ra_wrdata_lsw()                     _falcon_tsc_pmd_rde_reg(pa, 0xd206, __ERR)
#define wrc_micro_ra_wrdata_lsw(wr_val)               falcon_tsc_pmd_wr_reg(pa, 0xd206, wr_val)
#define rdc_micro_ra_wrdata_msw()                     _falcon_tsc_pmd_rde_reg(pa, 0xd207, __ERR)
#define wrc_micro_ra_wrdata_msw(wr_val)               falcon_tsc_pmd_wr_reg(pa, 0xd207, wr_val)
#define rdc_micro_ra_rdaddr_lsw()                     _falcon_tsc_pmd_rde_reg(pa, 0xd208, __ERR)
#define wrc_micro_ra_rdaddr_lsw(wr_val)               falcon_tsc_pmd_wr_reg(pa, 0xd208, wr_val)
#define rdc_micro_ra_rdaddr_msw()                     _falcon_tsc_pmd_rde_reg(pa, 0xd209, __ERR)
#define wrc_micro_ra_rdaddr_msw(wr_val)               falcon_tsc_pmd_wr_reg(pa, 0xd209, wr_val)
#define rdc_micro_ra_rddata_lsw()                     _falcon_tsc_pmd_rde_reg(pa, 0xd20a, __ERR)
#define rdc_micro_ra_rddata_msw()                     _falcon_tsc_pmd_rde_reg(pa, 0xd20b, __ERR)
#define rdc_micro_pramif_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd20c, 15, 15, __ERR)
#define wrc_micro_pramif_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd20c, 0x0001, 0, wr_val)
#define rdc_micro_pramif_ahb_wraddr_lsw()             _falcon_tsc_pmd_rde_field(pa, 0xd20d, 0, 2, __ERR)
#define wrc_micro_pramif_ahb_wraddr_lsw(wr_val)       falcon_tsc_pmd_mwr_reg(pa, 0xd20d, 0xfffc, 2, wr_val)
#define rdc_micro_pramif_ahb_wraddr_msw()             _falcon_tsc_pmd_rde_reg(pa, 0xd20e, __ERR)
#define wrc_micro_pramif_ahb_wraddr_msw(wr_val)       falcon_tsc_pmd_wr_reg(pa, 0xd20e, wr_val)
#define rdc_micro_pvt_tempdata_rmi()                  _falcon_tsc_pmd_rde_field(pa, 0xd210, 6, 6, __ERR)
#define rdc_micro_rmi_to_micro_mbox0()                _falcon_tsc_pmd_rde_reg(pa, 0xd211, __ERR)
#define wrc_micro_rmi_to_micro_mbox0(wr_val)          falcon_tsc_pmd_wr_reg(pa, 0xd211, wr_val)
#define rdc_micro_rmi_to_micro_mbox1()                _falcon_tsc_pmd_rde_reg(pa, 0xd212, __ERR)
#define wrc_micro_rmi_to_micro_mbox1(wr_val)          falcon_tsc_pmd_wr_reg(pa, 0xd212, wr_val)
#define rdc_micro_to_rmi_mbox0()                      _falcon_tsc_pmd_rde_reg(pa, 0xd213, __ERR)
#define rdc_micro_to_rmi_mbox1()                      _falcon_tsc_pmd_rde_reg(pa, 0xd214, __ERR)
#define rdc_micro_gen_intr_rmi_mbox1wr()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd215, 13, 15, __ERR)
#define wrc_micro_gen_intr_rmi_mbox1wr(wr_val)        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd215, 0x0004, 2, wr_val)
#define rdc_micro_gen_intr_rmi_mbox0wr()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd215, 14, 15, __ERR)
#define wrc_micro_gen_intr_rmi_mbox0wr(wr_val)        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd215, 0x0002, 1, wr_val)
#define rdc_micro_rmi_mbox_send_msgin()               _falcon_tsc_pmd_rde_field_byte(pa, 0xd215, 15, 15, __ERR)
#define wrc_micro_rmi_mbox_send_msgin(wr_val)         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd215, 0x0001, 0, wr_val)
#define rdc_micro_sw_pmi_hp_ext_rstb()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd216, 13, 15, __ERR)
#define wrc_micro_sw_pmi_hp_ext_rstb(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd216, 0x0004, 2, wr_val)
#define rdc_micro_sw_pmi_hp_rstb()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd216, 14, 15, __ERR)
#define wrc_micro_sw_pmi_hp_rstb(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd216, 0x0002, 1, wr_val)
#define rdc_micro_m0_hresp_en()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd216, 15, 15, __ERR)
#define wrc_micro_m0_hresp_en(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd216, 0x0001, 0, wr_val)
#define rdc_micro_pr_default_slave_error()            _falcon_tsc_pmd_rde_field_byte(pa, 0xd217, 13, 15, __ERR)
#define rdc_micro_rmi_default_slave_error()           _falcon_tsc_pmd_rde_field_byte(pa, 0xd217, 14, 15, __ERR)
#define rdc_micro_m0_default_slave_error()            _falcon_tsc_pmd_rde_field_byte(pa, 0xd217, 15, 15, __ERR)
#define rdc_micro_ra_autoinc_nxt_wraddr_lsw()         _falcon_tsc_pmd_rde_reg(pa, 0xd218, __ERR)
#define rdc_micro_ra_autoinc_nxt_rdaddr_lsw()         _falcon_tsc_pmd_rde_reg(pa, 0xd219, __ERR)
#define rdc_micro_pr_autoinc_nxt_wraddr_lsw()         _falcon_tsc_pmd_rde_reg(pa, 0xd21a, __ERR)
#define rdc_micro_pvt_tempdata_frc()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd21b, 3, 15, __ERR)
#define wrc_micro_pvt_tempdata_frc(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd21b, 0x1000, 12, wr_val)
#define rdc_micro_pvt_tempdata_frcval()               _falcon_tsc_pmd_rde_field(pa, 0xd21b, 6, 6, __ERR)
#define wrc_micro_pvt_tempdata_frcval(wr_val)         falcon_tsc_pmd_mwr_reg(pa, 0xd21b, 0x03ff, 0, wr_val)
#define rdc_micro_ecc_corrupt()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd220, 10, 14, __ERR)
#define wrc_micro_ecc_corrupt(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd220, 0x0030, 4, wr_val)
#define rdc_micro_ecc_frc_disable()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd220, 14, 15, __ERR)
#define wrc_micro_ecc_frc_disable(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd220, 0x0002, 1, wr_val)
#define rdc_micro_eccg_mode()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd220, 15, 15, __ERR)
#define wrc_micro_eccg_mode(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd220, 0x0001, 0, wr_val)
#define rdc_micro_ra_ecc_wrdata()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd221, 9, 9, __ERR)
#define wrc_micro_ra_ecc_wrdata(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd221, 0x007f, 0, wr_val)
#define rdc_micro_code_ram_ecc_address()              _falcon_tsc_pmd_rde_field(pa, 0xd222, 1, 1, __ERR)
#define rdc_micro_ra_ecc_rddata()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd223, 9, 9, __ERR)
#define rdc_micro_code_ram_tm()                       _falcon_tsc_pmd_rde_field(pa, 0xd224, 2, 2, __ERR)
#define wrc_micro_code_ram_tm(wr_val)                 falcon_tsc_pmd_mwr_reg(pa, 0xd224, 0x3fff, 0, wr_val)
#define rdc_micro_dr_size()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd225, 2, 10, __ERR)
#define wrc_micro_dr_size(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd225, 0x3f00, 8, wr_val)
#define rdc_micro_dr_looktab_en()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd225, 15, 15, __ERR)
#define wrc_micro_dr_looktab_en(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd225, 0x0001, 0, wr_val)
#define rdc_micro_rmi_m0_systemresetreq_status()      _falcon_tsc_pmd_rde_field_byte(pa, 0xd227, 6, 15, __ERR)
#define rdc_micro_rmi_m0_lockup_status()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd227, 7, 15, __ERR)
#define rdc_micro_rmi_ecc_multirow_err_status()       _falcon_tsc_pmd_rde_field_byte(pa, 0xd227, 9, 15, __ERR)
#define rdc_micro_rmi_ecc_uncorr_err_status()         _falcon_tsc_pmd_rde_field_byte(pa, 0xd227, 10, 15, __ERR)
#define rdc_micro_rmi_ecc_corr_err_status()           _falcon_tsc_pmd_rde_field_byte(pa, 0xd227, 11, 15, __ERR)
#define rdc_micro_rmi_mbox_msgout_status()            _falcon_tsc_pmd_rde_field_byte(pa, 0xd227, 15, 15, __ERR)
#define rdc_micro_rmi_m0_systemresetreq_intr_en()     _falcon_tsc_pmd_rde_field_byte(pa, 0xd226, 6, 15, __ERR)
#define wrc_micro_rmi_m0_systemresetreq_intr_en(wr_val)  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0200, 9, wr_val)
#define rdc_micro_rmi_m0_lockup_intr_en()             _falcon_tsc_pmd_rde_field_byte(pa, 0xd226, 7, 15, __ERR)
#define wrc_micro_rmi_m0_lockup_intr_en(wr_val)       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0100, 8, wr_val)
#define rdc_micro_rmi_ecc_multirow_err_intr_en()      _falcon_tsc_pmd_rde_field_byte(pa, 0xd226, 9, 15, __ERR)
#define wrc_micro_rmi_ecc_multirow_err_intr_en(wr_val)  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0040, 6, wr_val)
#define rdc_micro_rmi_ecc_uncorr_err_intr_en()        _falcon_tsc_pmd_rde_field_byte(pa, 0xd226, 10, 15, __ERR)
#define wrc_micro_rmi_ecc_uncorr_err_intr_en(wr_val)  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0020, 5, wr_val)
#define rdc_micro_rmi_ecc_corr_err_intr_en()          _falcon_tsc_pmd_rde_field_byte(pa, 0xd226, 11, 15, __ERR)
#define wrc_micro_rmi_ecc_corr_err_intr_en(wr_val)    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0010, 4, wr_val)
#define rdc_micro_rmi_mbox_msgout_intr_en()           _falcon_tsc_pmd_rde_field_byte(pa, 0xd226, 15, 15, __ERR)
#define wrc_micro_rmi_mbox_msgout_intr_en(wr_val)     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd226, 0x0001, 0, wr_val)
#define rdc_patt_gen_seq_0()                          _falcon_tsc_pmd_rde_reg(pa, 0xd120, __ERR)
#define wrc_patt_gen_seq_0(wr_val)                    falcon_tsc_pmd_wr_reg(pa, 0xd120, wr_val)
#define rdc_patt_gen_seq_1()                          _falcon_tsc_pmd_rde_reg(pa, 0xd121, __ERR)
#define wrc_patt_gen_seq_1(wr_val)                    falcon_tsc_pmd_wr_reg(pa, 0xd121, wr_val)
#define rdc_patt_gen_seq_2()                          _falcon_tsc_pmd_rde_reg(pa, 0xd122, __ERR)
#define wrc_patt_gen_seq_2(wr_val)                    falcon_tsc_pmd_wr_reg(pa, 0xd122, wr_val)
#define rdc_patt_gen_seq_3()                          _falcon_tsc_pmd_rde_reg(pa, 0xd123, __ERR)
#define wrc_patt_gen_seq_3(wr_val)                    falcon_tsc_pmd_wr_reg(pa, 0xd123, wr_val)
#define rdc_patt_gen_seq_4()                          _falcon_tsc_pmd_rde_reg(pa, 0xd124, __ERR)
#define wrc_patt_gen_seq_4(wr_val)                    falcon_tsc_pmd_wr_reg(pa, 0xd124, wr_val)
#define rdc_patt_gen_seq_5()                          _falcon_tsc_pmd_rde_reg(pa, 0xd125, __ERR)
#define wrc_patt_gen_seq_5(wr_val)                    falcon_tsc_pmd_wr_reg(pa, 0xd125, wr_val)
#define rdc_patt_gen_seq_6()                          _falcon_tsc_pmd_rde_reg(pa, 0xd126, __ERR)
#define wrc_patt_gen_seq_6(wr_val)                    falcon_tsc_pmd_wr_reg(pa, 0xd126, wr_val)
#define rdc_patt_gen_seq_7()                          _falcon_tsc_pmd_rde_reg(pa, 0xd127, __ERR)
#define wrc_patt_gen_seq_7(wr_val)                    falcon_tsc_pmd_wr_reg(pa, 0xd127, wr_val)
#define rdc_patt_gen_seq_8()                          _falcon_tsc_pmd_rde_reg(pa, 0xd128, __ERR)
#define wrc_patt_gen_seq_8(wr_val)                    falcon_tsc_pmd_wr_reg(pa, 0xd128, wr_val)
#define rdc_patt_gen_seq_9()                          _falcon_tsc_pmd_rde_reg(pa, 0xd129, __ERR)
#define wrc_patt_gen_seq_9(wr_val)                    falcon_tsc_pmd_wr_reg(pa, 0xd129, wr_val)
#define rdc_patt_gen_seq_10()                         _falcon_tsc_pmd_rde_reg(pa, 0xd12a, __ERR)
#define wrc_patt_gen_seq_10(wr_val)                   falcon_tsc_pmd_wr_reg(pa, 0xd12a, wr_val)
#define rdc_patt_gen_seq_11()                         _falcon_tsc_pmd_rde_reg(pa, 0xd12b, __ERR)
#define wrc_patt_gen_seq_11(wr_val)                   falcon_tsc_pmd_wr_reg(pa, 0xd12b, wr_val)
#define rdc_patt_gen_seq_12()                         _falcon_tsc_pmd_rde_reg(pa, 0xd12c, __ERR)
#define wrc_patt_gen_seq_12(wr_val)                   falcon_tsc_pmd_wr_reg(pa, 0xd12c, wr_val)
#define rdc_patt_gen_seq_13()                         _falcon_tsc_pmd_rde_reg(pa, 0xd12d, __ERR)
#define wrc_patt_gen_seq_13(wr_val)                   falcon_tsc_pmd_wr_reg(pa, 0xd12d, wr_val)
#define rdc_patt_gen_seq_14()                         _falcon_tsc_pmd_rde_reg(pa, 0xd12e, __ERR)
#define wrc_patt_gen_seq_14(wr_val)                   falcon_tsc_pmd_wr_reg(pa, 0xd12e, wr_val)
#define rdc_refclk_divcnt_sel()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd146, 13, 13, __ERR)
#define wrc_refclk_divcnt_sel(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd146, 0x0007, 0, wr_val)
#define rdc_rescal_in()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd149, 4, 12, __ERR)
#define rdc_cap_select()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd149, 8, 8, __ERR)
#define rdc_dbg_pll_state_one_hot()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd14a, 0, 8, __ERR)
#define rdc_dbg_cap_state_one_hot()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd14a, 8, 11, __ERR)
#define rdc_dbg_fdbck()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd14a, 13, 15, __ERR)
#define rdc_dbg_slowdn_change()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd14a, 14, 15, __ERR)
#define rdc_dbg_slowdn()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd14a, 15, 15, __ERR)
#define rdc_refclk_divcnt()                           _falcon_tsc_pmd_rde_field(pa, 0xd145, 2, 2, __ERR)
#define wrc_refclk_divcnt(wr_val)                     falcon_tsc_pmd_mwr_reg(pa, 0xd145, 0x3fff, 0, wr_val)
#define rdc_pll_seq_start()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 0, 15, __ERR)
#define wrc_pll_seq_start(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x8000, 15, wr_val)
#define rdc_vco_done_en()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 1, 15, __ERR)
#define wrc_vco_done_en(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x4000, 14, wr_val)
#define rdc_freq_det_retry_en()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 2, 15, __ERR)
#define wrc_freq_det_retry_en(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x2000, 13, wr_val)
#define rdc_freq_det_restart_en()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 3, 15, __ERR)
#define wrc_freq_det_restart_en(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x1000, 12, wr_val)
#define rdc_freq_monitor_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 4, 15, __ERR)
#define wrc_freq_monitor_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0800, 11, wr_val)
#define rdc_slowdn_xor()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 5, 15, __ERR)
#define wrc_slowdn_xor(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0400, 10, wr_val)
#define rdc_vco_rst_en()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 6, 15, __ERR)
#define wrc_vco_rst_en(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0200, 9, wr_val)
#define rdc_pll_force_fdone_en()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 7, 15, __ERR)
#define wrc_pll_force_fdone_en(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0100, 8, wr_val)
#define rdc_pll_force_fdone()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 8, 15, __ERR)
#define wrc_pll_force_fdone(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0080, 7, wr_val)
#define rdc_pll_force_fpass()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 9, 15, __ERR)
#define wrc_pll_force_fpass(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0040, 6, wr_val)
#define rdc_pll_force_cap_done_en()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 10, 15, __ERR)
#define wrc_pll_force_cap_done_en(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0020, 5, wr_val)
#define rdc_pll_force_cap_done()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 11, 15, __ERR)
#define wrc_pll_force_cap_done(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0010, 4, wr_val)
#define rdc_pll_force_cap_pass_en()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 12, 15, __ERR)
#define wrc_pll_force_cap_pass_en(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0008, 3, wr_val)
#define rdc_pll_force_cap_pass()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 13, 15, __ERR)
#define wrc_pll_force_cap_pass(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0004, 2, wr_val)
#define rdc_pll_lock_frc()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 14, 15, __ERR)
#define wrc_pll_lock_frc(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0002, 1, wr_val)
#define rdc_pll_lock_frc_val()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd144, 15, 15, __ERR)
#define wrc_pll_lock_frc_val(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd144, 0x0001, 0, wr_val)
#define rdc_vco_range_adjust()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd147, 2, 11, __ERR)
#define wrc_vco_range_adjust(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd147, 0x3e00, 9, wr_val)
#define rdc_rescal_frc()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd147, 7, 15, __ERR)
#define wrc_rescal_frc(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd147, 0x0100, 8, wr_val)
#define rdc_rescal_frc_val()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd147, 8, 12, __ERR)
#define wrc_rescal_frc_val(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd147, 0x00f0, 4, wr_val)
#define rdc_pll_mode()                                _falcon_tsc_pmd_rde_field_byte(pa, 0xd147, 12, 12, __ERR)
#define wrc_pll_mode(wr_val)                          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd147, 0x000f, 0, wr_val)
#define rdc_cap_select_m()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd143, 0, 8, __ERR)
#define wrc_cap_select_m(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0xff00, 8, wr_val)
#define rdc_cap_select_m_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd143, 8, 15, __ERR)
#define wrc_cap_select_m_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0080, 7, wr_val)
#define rdc_cap_force_slowdown_en()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd143, 9, 15, __ERR)
#define wrc_cap_force_slowdown_en(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0040, 6, wr_val)
#define rdc_cap_force_slowdown()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd143, 10, 15, __ERR)
#define wrc_cap_force_slowdown(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0020, 5, wr_val)
#define rdc_cap_retry_en()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd143, 11, 15, __ERR)
#define wrc_cap_retry_en(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0010, 4, wr_val)
#define rdc_cap_restart()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd143, 12, 15, __ERR)
#define wrc_cap_restart(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0008, 3, wr_val)
#define rdc_cap_seq_cya()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd143, 13, 15, __ERR)
#define wrc_cap_seq_cya(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0004, 2, wr_val)
#define rdc_cap_cnt_mask_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd143, 14, 15, __ERR)
#define wrc_cap_cnt_mask_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0002, 1, wr_val)
#define rdc_fast_search_mode()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd143, 15, 15, __ERR)
#define wrc_fast_search_mode(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd143, 0x0001, 0, wr_val)
#define rdc_lost_pll_lock_sm()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 0, 15, __ERR)
#define rdc_cap_done()                                _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 1, 15, __ERR)
#define rdc_cap_pass()                                _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 2, 15, __ERR)
#define rdc_freq_done_sm()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 3, 15, __ERR)
#define rdc_freq_pass_sm()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 4, 15, __ERR)
#define rdc_pll_seq_done()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 5, 15, __ERR)
#define rdc_pll_seq_pass()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 6, 15, __ERR)
#define rdc_pll_lock()                                _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 7, 15, __ERR)
#define rdc_cap_done_lh_ll()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 9, 15, __ERR)
#define rdc_cap_pass_lh_ll()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 10, 15, __ERR)
#define rdc_freq_done_sm_lh_ll()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 11, 15, __ERR)
#define rdc_freq_pass_sm_lh_ll()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 12, 15, __ERR)
#define rdc_pll_seq_done_lh_ll()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 13, 15, __ERR)
#define rdc_pll_seq_pass_lh_ll()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 14, 15, __ERR)
#define rdc_pll_lock_lh_ll()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd148, 15, 15, __ERR)
#define rdc_res_cal_cntr()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd142, 0, 8, __ERR)
#define wrc_res_cal_cntr(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd142, 0xff00, 8, wr_val)
#define rdc_win_cal_cntr()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd142, 8, 8, __ERR)
#define wrc_win_cal_cntr(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd142, 0x00ff, 0, wr_val)
#define rdc_pre_freq_det_time()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd141, 0, 8, __ERR)
#define wrc_pre_freq_det_time(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd141, 0xff00, 8, wr_val)
#define rdc_retry_time()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd141, 8, 8, __ERR)
#define wrc_retry_time(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd141, 0x00ff, 0, wr_val)
#define rdc_vco_start_time()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd140, 0, 8, __ERR)
#define wrc_vco_start_time(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd140, 0xff00, 8, wr_val)
#define rdc_vco_step_time()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd140, 8, 8, __ERR)
#define wrc_vco_step_time(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd140, 0x00ff, 0, wr_val)
#define rd_signal_detect_filter_count()               _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e0, 11, 11, __ERR)
#define wr_signal_detect_filter_count(wr_val)         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e0, 0x001f, 0, wr_val)
#define rd_los_filter_count()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e0, 3, 11, __ERR)
#define wr_los_filter_count(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e0, 0x1f00, 8, wr_val)
#define rd_energy_detect_mask_count()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e1, 0, 11, __ERR)
#define wr_energy_detect_mask_count(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0xf800, 11, wr_val)
#define rd_afe_signal_detect_dis()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e1, 15, 15, __ERR)
#define wr_afe_signal_detect_dis(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0001, 0, wr_val)
#define rd_ext_los_en()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e1, 14, 15, __ERR)
#define wr_ext_los_en(wr_val)                         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0002, 1, wr_val)
#define rd_ext_los_inv()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e1, 13, 15, __ERR)
#define wr_ext_los_inv(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0004, 2, wr_val)
#define rd_ignore_lp_mode()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e1, 12, 15, __ERR)
#define wr_ignore_lp_mode(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0008, 3, wr_val)
#define rd_signal_detect_filter_1us()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e1, 11, 15, __ERR)
#define wr_signal_detect_filter_1us(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0010, 4, wr_val)
#define rd_energy_detect_frc()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e1, 10, 15, __ERR)
#define wr_energy_detect_frc(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0020, 5, wr_val)
#define rd_energy_detect_frc_val()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e1, 9, 15, __ERR)
#define wr_energy_detect_frc_val(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0040, 6, wr_val)
#define rd_signal_detect_frc()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e1, 8, 15, __ERR)
#define wr_signal_detect_frc(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0080, 7, wr_val)
#define rd_signal_detect_frc_val()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e1, 7, 15, __ERR)
#define wr_signal_detect_frc_val(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e1, 0x0100, 8, wr_val)
#define rd_los_thresh()                               _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e2, 13, 13, __ERR)
#define wr_los_thresh(wr_val)                         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e2, 0x0007, 0, wr_val)
#define rd_signal_detect_thresh()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e2, 9, 13, __ERR)
#define wr_signal_detect_thresh(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e2, 0x0070, 4, wr_val)
#define rd_hold_los_count()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e2, 5, 13, __ERR)
#define wr_hold_los_count(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e2, 0x0700, 8, wr_val)
#define rd_hold_sd_count()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e2, 2, 13, __ERR)
#define wr_hold_sd_count(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0e2, 0x3800, 11, wr_val)
#define rd_signal_detect()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e8, 15, 15, __ERR)
#define rd_signal_detect_change()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e8, 14, 15, __ERR)
#define rd_energy_detect()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e8, 13, 15, __ERR)
#define rd_energy_detect_change()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e8, 12, 15, __ERR)
#define rd_signal_detect_raw()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e8, 11, 15, __ERR)
#define rd_signal_detect_raw_change()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e8, 10, 15, __ERR)
#define rd_afe_sigdet_thresh()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0e8, 5, 13, __ERR)
#define rd_prbs_chk_clk_en_frc_on()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd161, 4, 15, __ERR)
#define wr_prbs_chk_clk_en_frc_on(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0800, 11, wr_val)
#define rd_trnsum_error_count_en()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd161, 5, 15, __ERR)
#define wr_trnsum_error_count_en(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0400, 10, wr_val)
#define rd_prbs_chk_err_cnt_burst_mode()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd161, 6, 15, __ERR)
#define wr_prbs_chk_err_cnt_burst_mode(wr_val)        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0200, 9, wr_val)
#define rd_prbs_burst_len_chk_en()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd161, 7, 15, __ERR)
#define wr_prbs_burst_len_chk_en(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0100, 8, wr_val)
#define rd_prbs_chk_en_auto_mode()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd161, 8, 15, __ERR)
#define wr_prbs_chk_en_auto_mode(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0080, 7, wr_val)
#define rd_prbs_chk_mode()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd161, 9, 14, __ERR)
#define wr_prbs_chk_mode(wr_val)                      _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0060, 5, wr_val)
#define rd_prbs_chk_inv()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd161, 11, 15, __ERR)
#define wr_prbs_chk_inv(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0010, 4, wr_val)
#define rd_prbs_chk_mode_sel()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd161, 12, 13, __ERR)
#define wr_prbs_chk_mode_sel(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x000e, 1, wr_val)
#define rd_prbs_chk_en()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd161, 15, 15, __ERR)
#define wr_prbs_chk_en(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd161, 0x0001, 0, wr_val)
#define rd_prbs_chk_lock_cnt()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd160, 11, 11, __ERR)
#define wr_prbs_chk_lock_cnt(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd160, 0x001f, 0, wr_val)
#define rd_prbs_chk_ool_cnt()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd160, 3, 11, __ERR)
#define wr_prbs_chk_ool_cnt(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd160, 0x1f00, 8, wr_val)
#define rd_dig_lpbk_pd_bias_en()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd162, 12, 15, __ERR)
#define wr_dig_lpbk_pd_bias_en(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd162, 0x0008, 3, wr_val)
#define rd_dig_lpbk_pd_mode()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd162, 14, 15, __ERR)
#define wr_dig_lpbk_pd_mode(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd162, 0x0002, 1, wr_val)
#define rd_dig_lpbk_en()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd162, 15, 15, __ERR)
#define wr_dig_lpbk_en(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd162, 0x0001, 0, wr_val)
#define rd_tlb_rx_diff_dec_en()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd163, 12, 15, __ERR)
#define wr_tlb_rx_diff_dec_en(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd163, 0x0008, 3, wr_val)
#define rd_dbg_mask_dig_lpbk_en()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd163, 13, 15, __ERR)
#define wr_dbg_mask_dig_lpbk_en(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd163, 0x0004, 2, wr_val)
#define rd_rx_pmd_dp_invert()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd163, 15, 15, __ERR)
#define wr_rx_pmd_dp_invert(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd163, 0x0001, 0, wr_val)
#define rd_prbs_chk_en_timeout()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd164, 3, 11, __ERR)
#define wr_prbs_chk_en_timeout(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd164, 0x1f00, 8, wr_val)
#define rd_prbs_chk_en_timer_mode()                   _falcon_tsc_pmd_rde_field_byte(pa, 0xd164, 14, 14, __ERR)
#define wr_prbs_chk_en_timer_mode(wr_val)             _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd164, 0x0003, 0, wr_val)
#define rd_dig_lpbk_pd_early_ind()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd168, 14, 15, __ERR)
#define rd_dig_lpbk_pd_late_ind()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd168, 15, 15, __ERR)
#define rd_prbs_chk_lock()                            _falcon_tsc_pmd_rde_field_byte(pa, 0xd169, 15, 15, __ERR)
#define rd_prbs_chk_lock_lost_lh()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd16a, 0, 15, __ERR)
#define rd_prbs_chk_err_cnt_msb()                     _falcon_tsc_pmd_rde_field(pa, 0xd16a, 1, 1, __ERR)
#define rd_prbs_chk_err_cnt_lsb()                     _falcon_tsc_pmd_rde_reg(pa, 0xd16b, __ERR)
#define rd_pmd_rx_lock()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd16c, 15, 15, __ERR)
#define rd_pmd_rx_lock_change()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd16c, 14, 15, __ERR)
#define rd_prbs_burst_err_length_status()             _falcon_tsc_pmd_rde_field_byte(pa, 0xd16d, 10, 10, __ERR)
#define rd_max_prbs_burst_err_length_status()         _falcon_tsc_pmd_rde_field_byte(pa, 0xd16e, 10, 10, __ERR)
#define rd_patt_gen_start_pos()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd170, 0, 12, __ERR)
#define wr_patt_gen_start_pos(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd170, 0xf000, 12, wr_val)
#define rd_patt_gen_stop_pos()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd170, 4, 12, __ERR)
#define wr_patt_gen_stop_pos(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd170, 0x0f00, 8, wr_val)
#define rd_patt_gen_en()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd170, 15, 15, __ERR)
#define wr_patt_gen_en(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd170, 0x0001, 0, wr_val)
#define rd_prbs_gen_err_ins()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd171, 10, 15, __ERR)
#define wr_prbs_gen_err_ins(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd171, 0x0020, 5, wr_val)
#define rd_prbs_gen_inv()                             _falcon_tsc_pmd_rde_field_byte(pa, 0xd171, 11, 15, __ERR)
#define wr_prbs_gen_inv(wr_val)                       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd171, 0x0010, 4, wr_val)
#define rd_prbs_gen_mode_sel()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd171, 12, 13, __ERR)
#define wr_prbs_gen_mode_sel(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd171, 0x000e, 1, wr_val)
#define rd_prbs_gen_en()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd171, 15, 15, __ERR)
#define wr_prbs_gen_en(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd171, 0x0001, 0, wr_val)
#define rd_rmt_lpbk_pd_frc_on()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd172, 13, 15, __ERR)
#define wr_rmt_lpbk_pd_frc_on(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd172, 0x0004, 2, wr_val)
#define rd_rmt_lpbk_pd_mode()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd172, 14, 15, __ERR)
#define wr_rmt_lpbk_pd_mode(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd172, 0x0002, 1, wr_val)
#define rd_rmt_lpbk_en()                              _falcon_tsc_pmd_rde_field_byte(pa, 0xd172, 15, 15, __ERR)
#define wr_rmt_lpbk_en(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd172, 0x0001, 0, wr_val)
#define rd_tlb_tx_diff_enc_en()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd173, 12, 15, __ERR)
#define wr_tlb_tx_diff_enc_en(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd173, 0x0008, 3, wr_val)
#define rd_tx_mux_sel_order()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd173, 13, 15, __ERR)
#define wr_tx_mux_sel_order(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd173, 0x0004, 2, wr_val)
#define rd_tx_pcs_native_ana_frmt_en()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd173, 14, 15, __ERR)
#define wr_tx_pcs_native_ana_frmt_en(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd173, 0x0002, 1, wr_val)
#define rd_tx_pmd_dp_invert()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd173, 15, 15, __ERR)
#define wr_tx_pmd_dp_invert(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd173, 0x0001, 0, wr_val)
#define rd_rmt_lpbk_pd_early_ind()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd178, 14, 15, __ERR)
#define rd_rmt_lpbk_pd_late_ind()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd178, 15, 15, __ERR)
#define rd_txfir_post_offset()                        _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd130, 4, 12, __ERR)
#define wr_txfir_post_offset(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd130, 0x0f00, 8, wr_val)
#define rd_txfir_main_offset()                        _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd130, 8, 12, __ERR)
#define wr_txfir_main_offset(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd130, 0x00f0, 4, wr_val)
#define rd_txfir_pre_offset()                         _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd130, 12, 12, __ERR)
#define wr_txfir_pre_offset(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd130, 0x000f, 0, wr_val)
#define rd_txfir_post2_offset()                       _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd131, 4, 12, __ERR)
#define wr_txfir_post2_offset(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd131, 0x0f00, 8, wr_val)
#define rd_txfir_post2()                              _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd131, 11, 11, __ERR)
#define wr_txfir_post2(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd131, 0x001f, 0, wr_val)
#define rd_txfir_post3_offset()                       _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd132, 4, 12, __ERR)
#define wr_txfir_post3_offset(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd132, 0x0f00, 8, wr_val)
#define rd_txfir_post3()                              _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd132, 12, 12, __ERR)
#define wr_txfir_post3(wr_val)                        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd132, 0x000f, 0, wr_val)
#define rd_txfir_post_after_ovr()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd133, 2, 10, __ERR)
#define rd_txfir_pre_after_ovr()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd133, 11, 11, __ERR)
#define rd_txfir_main_after_ovr()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd134, 9, 9, __ERR)
#define rd_txfir_post_adjusted()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd135, 2, 10, __ERR)
#define rd_txfir_pre_adjusted()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd135, 11, 11, __ERR)
#define rd_txfir_post2_adjusted()                     _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd136, 3, 11, __ERR)
#define rd_txfir_main_adjusted()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd136, 9, 9, __ERR)
#define rd_txfir_post3_adjusted()                     _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd137, 12, 12, __ERR)
#define rd_micro_tx_disable()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd138, 15, 15, __ERR)
#define wr_micro_tx_disable(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd138, 0x0001, 0, wr_val)
#define rd_dp_reset_tx_disable_dis()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd139, 3, 15, __ERR)
#define wr_dp_reset_tx_disable_dis(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd139, 0x1000, 12, wr_val)
#define rd_tx_disable_output_sel()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd139, 4, 14, __ERR)
#define wr_tx_disable_output_sel(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd139, 0x0c00, 10, wr_val)
#define rd_tx_eee_alert_en()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd139, 6, 15, __ERR)
#define wr_tx_eee_alert_en(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd139, 0x0200, 9, wr_val)
#define rd_tx_eee_quiet_en()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd139, 7, 15, __ERR)
#define wr_tx_eee_quiet_en(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd139, 0x0100, 8, wr_val)
#define rd_tx_disable_timer_ctrl()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd139, 8, 10, __ERR)
#define wr_tx_disable_timer_ctrl(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd139, 0x00fc, 2, wr_val)
#define rd_pmd_tx_disable_pkill()                     _falcon_tsc_pmd_rde_field_byte(pa, 0xd139, 14, 15, __ERR)
#define wr_pmd_tx_disable_pkill(wr_val)               _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd139, 0x0002, 1, wr_val)
#define rd_sdk_tx_disable()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd139, 15, 15, __ERR)
#define wr_sdk_tx_disable(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd139, 0x0001, 0, wr_val)
#define rdc_tx_pi_en()                                _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a0, 15, 15, __ERR)
#define wrc_tx_pi_en(wr_val)                          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0001, 0, wr_val)
#define rdc_tx_pi_jitter_filter_en()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a0, 14, 15, __ERR)
#define wrc_tx_pi_jitter_filter_en(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0002, 1, wr_val)
#define rdc_tx_pi_ext_ctrl_en()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a0, 13, 15, __ERR)
#define wrc_tx_pi_ext_ctrl_en(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0004, 2, wr_val)
#define rdc_tx_pi_freq_override_en()                  _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a0, 12, 15, __ERR)
#define wrc_tx_pi_freq_override_en(wr_val)            _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0008, 3, wr_val)
#define rdc_tx_pi_sj_gen_en()                         _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a0, 11, 15, __ERR)
#define wrc_tx_pi_sj_gen_en(wr_val)                   _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0010, 4, wr_val)
#define rdc_tx_pi_ssc_gen_en()                        _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a0, 10, 15, __ERR)
#define wrc_tx_pi_ssc_gen_en(wr_val)                  _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0020, 5, wr_val)
#define rdc_tx_pi_jit_ssc_freq_mode()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a0, 9, 15, __ERR)
#define wrc_tx_pi_jit_ssc_freq_mode(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0040, 6, wr_val)
#define rdc_tx_pi_second_order_loop_en()              _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a0, 8, 15, __ERR)
#define wrc_tx_pi_second_order_loop_en(wr_val)        _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0080, 7, wr_val)
#define rdc_tx_pi_first_order_bwsel_integ()           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a0, 6, 14, __ERR)
#define wrc_tx_pi_first_order_bwsel_integ(wr_val)     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0300, 8, wr_val)
#define rdc_tx_pi_second_order_bwsel_integ()          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a0, 4, 14, __ERR)
#define wrc_tx_pi_second_order_bwsel_integ(wr_val)    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x0c00, 10, wr_val)
#define rdc_tx_pi_ext_phase_bwsel_integ()             _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a0, 1, 13, __ERR)
#define wrc_tx_pi_ext_phase_bwsel_integ(wr_val)       _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a0, 0x7000, 12, wr_val)
#define rdc_tx_pi_freq_override_val()                 _falcon_tsc_pmd_rde_field_signed(pa, 0xd0a1, 1, 1, __ERR)
#define wrc_tx_pi_freq_override_val(wr_val)           falcon_tsc_pmd_mwr_reg(pa, 0xd0a1, 0x7fff, 0, wr_val)
#define rdc_tx_pi_jit_freq_idx()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a2, 10, 10, __ERR)
#define wrc_tx_pi_jit_freq_idx(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a2, 0x003f, 0, wr_val)
#define rdc_tx_pi_jit_amp()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a2, 2, 10, __ERR)
#define wrc_tx_pi_jit_amp(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a2, 0x3f00, 8, wr_val)
#define rdc_tx_pi_phase_override()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a3, 15, 15, __ERR)
#define wrc_tx_pi_phase_override(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a3, 0x0001, 0, wr_val)
#define rdc_tx_pi_phase_strobe()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a3, 14, 15, __ERR)
#define wrc_tx_pi_phase_strobe(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a3, 0x0002, 1, wr_val)
#define rdc_tx_pi_phase_step_dir()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a3, 13, 15, __ERR)
#define wrc_tx_pi_phase_step_dir(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a3, 0x0004, 2, wr_val)
#define rdc_tx_pi_phase_invert()                      _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a3, 11, 15, __ERR)
#define wrc_tx_pi_phase_invert(wr_val)                _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a3, 0x0010, 4, wr_val)
#define rdc_tx_pi_phase_step_num()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a3, 4, 12, __ERR)
#define wrc_tx_pi_phase_step_num(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a3, 0x0f00, 8, wr_val)
#define rdc_tx_pi_frz_frc()                           _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a4, 15, 15, __ERR)
#define wrc_tx_pi_frz_frc(wr_val)                     _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a4, 0x0001, 0, wr_val)
#define rdc_tx_pi_frz_frc_val()                       _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a4, 14, 15, __ERR)
#define wrc_tx_pi_frz_frc_val(wr_val)                 _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a4, 0x0002, 1, wr_val)
#define rdc_tx_pi_frz_mode()                          _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a4, 13, 15, __ERR)
#define wrc_tx_pi_frz_mode(wr_val)                    _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a4, 0x0004, 2, wr_val)
#define rdc_tx_pi_reset_code_dbg()                    _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a4, 12, 15, __ERR)
#define wrc_tx_pi_reset_code_dbg(wr_val)              _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a4, 0x0008, 3, wr_val)
#define rdc_tx_pi_rmt_lpbk_bypass_flt()               _falcon_tsc_pmd_rde_field_byte(pa, 0xd0a4, 11, 15, __ERR)
#define wrc_tx_pi_rmt_lpbk_bypass_flt(wr_val)         _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd0a4, 0x0010, 4, wr_val)
#define rdc_tx_pi_phase_cntr()                        _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd0a8, 9, 9, __ERR)
#define rdc_tx_pi_integ1_reg()                        _falcon_tsc_pmd_rde_field_signed(pa, 0xd0a9, 2, 2, __ERR)
#define rdc_tx_pi_integ2_reg()                        _falcon_tsc_pmd_rde_field_signed(pa, 0xd0aa, 1, 1, __ERR)
#define rdc_tx_pi_phase_err()                         _falcon_tsc_pmd_rde_field_signed_byte(pa, 0xd0ab, 10, 10, __ERR)
#define rdc_txcom_pre_tap_alert_val()                 _falcon_tsc_pmd_rde_field_byte(pa, 0xd150, 3, 11, __ERR)
#define wrc_txcom_pre_tap_alert_val(wr_val)           _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd150, 0x1f00, 8, wr_val)
#define rdc_txcom_post_tap_alert_val()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd150, 10, 10, __ERR)
#define wrc_txcom_post_tap_alert_val(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd150, 0x003f, 0, wr_val)
#define rdc_txcom_main_tap_alert_val()                _falcon_tsc_pmd_rde_field_byte(pa, 0xd151, 9, 9, __ERR)
#define wrc_txcom_main_tap_alert_val(wr_val)          _falcon_tsc_pmd_mwr_reg_byte(pa, 0xd151, 0x007f, 0, wr_val)
#define rdc_txcom_cl93n72_max_wait_timer_period()     _falcon_tsc_pmd_rde_reg(pa, 0xd152, __ERR)
#define wrc_txcom_cl93n72_max_wait_timer_period(wr_val)  falcon_tsc_pmd_wr_reg(pa, 0xd152, wr_val)
#define rdc_txcom_cl93n72_wait_cntr_limit()           _falcon_tsc_pmd_rde_field(pa, 0xd153, 7, 7, __ERR)
#define wrc_txcom_cl93n72_wait_cntr_limit(wr_val)     falcon_tsc_pmd_mwr_reg(pa, 0xd153, 0x01ff, 0, wr_val)

#endif
